Synchronous semiconductor memory device operable in a plurality of data write operation modes
First Claim
1. A synchronous semiconductor memory device operable in synchronization with an externally applied external clock signal having a predetermined width, comprising:
- a memory array having a plurality of memory cells;
internal clock generating means receiving said externally applied external clock signal, for generating an internal clock signal determining a data write cycle in synchronization with said external clock signal; and
data write means for writing data into a selected memory cell in said memory array in synchronization with said internal clock signal in data writing mode of operation, said data write means being operable in a pipelined mode for writing different data into different memory cells every cycle of said internal clock signal and a prefetch mode for writing different data into a plurality of memory cells every multiple cycles of said internal clock signal;
a mode register for storing data determining an operation mode of said data write means; and
mode setting means for setting the operation mode of said data write means to either of the pipelined mode and the prefetch mode in accordance with the data stored in said mode register.
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Accused Products
Abstract
A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.
78 Citations
6 Claims
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1. A synchronous semiconductor memory device operable in synchronization with an externally applied external clock signal having a predetermined width, comprising:
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a memory array having a plurality of memory cells; internal clock generating means receiving said externally applied external clock signal, for generating an internal clock signal determining a data write cycle in synchronization with said external clock signal; and data write means for writing data into a selected memory cell in said memory array in synchronization with said internal clock signal in data writing mode of operation, said data write means being operable in a pipelined mode for writing different data into different memory cells every cycle of said internal clock signal and a prefetch mode for writing different data into a plurality of memory cells every multiple cycles of said internal clock signal; a mode register for storing data determining an operation mode of said data write means; and mode setting means for setting the operation mode of said data write means to either of the pipelined mode and the prefetch mode in accordance with the data stored in said mode register. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification