Duobinary coding and modulation technique for optical communication systems

• US 5,892,858 A
• Filed: 03/27/1997
• Issued: 04/06/1999
• Est. Priority Date: 03/27/1997
• Status: Expired due to Term

• Current Assignee: Ciena Corporation, Ciena Luxembourg S.a.r.l. (Ciena Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Taraschuk, Terry W. B., Vaziri, Mazoud, Solheim, Alan Glen, O'Sullivan, Maurice S., Roberts, Kim Byron
• Primary Examiner(s): NGO, HUNG NHAT
• Application Number:
  US08/827,419
• Time in Patent Office: 740 Days
• Field of Search: 341/56, 341/57, 385/2, 385/3, 385/8, 385/9, 385/24
• US Class Current: 385/2
• CPC Class Codes: H03M 5/18 two levels being symmetrical with respect to the third level, i.e. balanced bipolar ternary code
• CPC Class Codes: H04B 10/505 using external modulation
• CPC Class Codes: H04B 10/5055 using a pre-coder
• CPC Class Codes: H04B 10/5167 Duo-binary; Alternative mark inversion; Phase shaped binary transmission

Abstract

A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit y_k =0 when the corresponding bit x_k =0; bits y_k alternatively assume a logical level "+1" and "-1" whenever an input bit x_k-1 =0 changes to x_k =1, and the output bit y_k maintains the logical level "+1" or "-1" whenever the corresponding bit x_k maintains the logical level "1". A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1) is also provided, comprising a D-type flip-flop for generating a binary switch signal. A first AND circuit receives the input sequence and the switch signal, and provides a first binary sequence a(0,1), while a second AND circuit receives the input sequence and the complement of the switch signal and provides a second binary sequence b(0,1). These first and second binary sequences are applied to a summer to obtain the output sequence y(+1,0,-1). A method for differentially driving a M-Z modulator using a virtual ground level is also provided, which reduces the peak-to-peak drive voltage by a factor of two.

Claims

1. A method for encoding a binary input sequence x(n,d) to obtain a duobinary output sequence y(+d,n,-d), comprising the steps of:

providing a first logical level "n" for a bit y_k of said duobinary output sequence y(+d,n,-d) when a corresponding bit x_k of said binary input sequence x(n,d) has said first logic level "n";

switching a bit y_k of said duobinary output sequence y(+d,n,-d) from said first level "n" to alternatively assume one of a second "+d" and a third "-d" logical level, whenever a succession x_k-1, x_k of bits in said input sequence x(n,d) comprises a change from said first logical level "n" to said second logical level "d"; and

maintaining the logical level of a bit y_k as one of said second +d" and said third "-d" logical level, whenever a corresponding bit x_k maintains said second logical level "d" and whenever a succession x_k-1, x_k of bits said input sequence x(n,d) comprises a change from said second logical level "n" to said first logical level "d".

2. A method as claimed in claim 1, wherein said first logical level "n" is logic "0", said second logical level "d" is logic "+1" and said third logical level "-d" is "-1".

3. A method as claimed in claim 1, wherein said first logical level "n" is logic "1", said second logical level "d" is logic "0" and said third logical level "-d" is "-0".

4. A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1), comprising the steps of:

preparing from said input sequence x(0,1) a binary switch signal Q(0,1) which maintains a current logical value when the input sequence x(0,1) comprises one of;

a succession of bits x_k =0, a succession of bits x_k =1, and a succession of bits x_k =0, x_k =1, and switches to the opposite logical value when the input sequence x(0,1) comprises a succession of bits x_k =1, x_k+1 =0;

logically adding said binary input sequence x(0,1) and said switch signal Q(0,1) to obtain a first binary sequence a(0,1);

logically adding said binary input sequence x(0,1) and the complement Q(1,0) of said switch signal to obtain a second binary sequence b(0,1); and

summing said first and second binary sequences for obtaining said duobinary output sequence y(+1,0,-1).

5. A method as claimed in claim 4, wherein said step of preparing comprises the sub-steps of:

providing a D-type flip-flop having a clock input, an input D, an output Q and an output Q;

connecting said output Q to said input D of said D-type flip-flop;

applying said input sequence x(0,1) to the clock input; and

collecting said switch signal on said output Q of said D-type flip-flop.

6. A method as claimed in claim 4, wherein said step of summing comprises adding the level corresponding to a bit a_k of said first binary sequence a(0,1) with the level corresponding to a bit b_k of said second binary sequence b(0,1).

7. A method as claimed in claim 4, further comprising the steps of generating a driving signal from said output sequence y(+1,0,-1).

8. A method as claimed in claim 7, further comprising the steps of:

providing an external modulator having a first and a second travelling wave-guide, a splitter between an input port and said first and second travelling wave-guides, a combiner between said first and second travelling wave-guides and an output port, a first and a second travelling wave electrode, each associated with said respective first and second travelling wave-guide, and a control electrode;

ac coupling said driving signal to an external modulator; and

modulating a continuous wave (CW) optical carrier signal with said driving signal using said external modulator.

9. A method as claimed in claim 8, wherein said external modulator is a Mach-Zehnder interferometer and said step of modulating comprises:

aligning said input port to provide said CW optical carrier signal at said input port of said Mach-Zehnder interferometer; and

aligning said output port to couple a duobinary modulated optical signal into an optical fiber.

10. A method as claimed in claim 8, wherein said step of modulating comprises:

applying a bias voltage V_Bias between said first and said second travelling wave electrodes; and

applying said driving signal to said control electrode.

11. A method as claimed in claim 4, further comprising the steps of generating a differential driving signal from said output sequence y(+1,0,-1), said differential driving signal comprising a driving signal and a complementary driving signal.

12. A method as claimed in claim 11, further comprising the steps of:

providing an external modulator having a first and a second travelling wave-guide, a splitter between an input port and said first and second travelling wave-guides, a combiner between said first and second travelling wave-guides and an output port, a first and a second travelling wave electrode, each associated with said respective first and second travelling wave-guide;

ac coupling said driving signal to an external modulator; and

modulating a continuous wave (CW) optical carrier signal with said driving signal using said external modulator.

13. A method as claimed in claim 12, wherein said step of modulating comprises:

connecting a first end of a first impedance to a combiner side of said first travelling wave electrode and connecting a second end of said first impedance to ground;

connecting a first end of a second impedance to a combiner side of said second travelling wave electrode and connecting a second end of said second impedance to ground;

applying said driving signal to a splitter side of said first travelling wave electrode and applying said complementary driving signal to a splitter side of said second travelling wave electrode; and

adjusting the value of said first and second impedances to obtain a virtual ground for said driving signal and said complementary driving signal.

14. A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1), comprising:

means for generating a binary switch signal Q(0,1);

a first AND circuit for receiving said binary input sequence x(0,1) and said switch signal Q(0,1), and providing a first binary sequence a(0,1);

a second AND circuit for receiving said binary input sequence x(0,1) and the complement Q(1,0) of said switch signal to obtain a second binary sequence b(0,1); and

a summer for processing said first and second binary sequences to obtain said output sequence y(+1,0,-1) on an output terminal.

15. A device as claimed in claim 14, wherein said means for generating is a D-type flip-flop having a clock input, an input D, an output Q and an output Q, for receiving said binary input sequence x(0,1) on the clock input, and said output Q connected to said input D.

16. A device as claimed in claim 14, wherein said summer comprises:

a load arranged between said output terminal and the ground;

a first switching device having the collector connected to said output terminal, the emitter connected to a first current source, and the base connected to receive said first binary sequence a(0,1);

an inverter for receiving said second binary sequence b(0,1) and proving an inverted binary sequence; and

a second switching device having the collector connected to said output terminal, the emitter connected to a second current source, and the base connected to said inverter, wherein said first and said second current sources are connected to a supply voltage.

17. A device as claimed in claim 14, further comprising a driver for receiving said duobinary output sequence y(+1,0,-1) and providing a driving signal.

18. A device as claimed in claim 14, further comprising a pair of differential drivers for receiving said duobinary output sequence y(+1,0,-1) and providing a differential signal comprising a modulating signal and a complementary modulating signal.

19. A Mach-Zehnder (M-Z) interferometer for modulating a continuous wave (CW) optical carrier with a duobinary encoded driving signal, said M-Z interferometer having a first and a second travelling wave-guide, a splitter between an input port and said first and second travelling wave-guides, a combiner between said first and second travelling wave-guides and an output port, a first and a second travelling wave electrode, each associated with said respective first and second travelling wave-guide, and a control electrode, said M-Z interferometer further comprising:

means for applying a bias voltage V_Bias between said first and said second travelling wave electrode;

means for providing said duobinary encoded driving signal to said control electrode;

means for coupling said CW optical carrier signal to said input port; and

means for coupling a duobinary modulated optical signal from said output port into an optical fiber.

20. A Mach-Zehnder (M-Z) interferometer for modulating a continuous wave (CW) optical carrier with a duobinary encoded differential driving signal, said M-Z interferometer having a first and a second travelling wave-guide, a splitter between an input port and said first and second travelling wave-guides, a combiner between said first and second travelling wave-guides and an output port, a first and a second travelling wave electrode, each associated with said respective first and second travelling wave-guide, said M-Z interferometer further comprising:

means for applying said modulating signal to a splitter side of said first travelling wave electrode and for applying said complementary modulating signal to a splitter side of said second travelling wave electrode;

a first matched impedance for connection with a first end to a combiner side of said first travelling wave electrode and with a second end to ground;

a second matched impedance for connection with a first end to a combiner side of said second travelling wave electrode and with a second end to ground;

means for coupling said CW optical carrier signal to said input port; and

means for coupling a duobinary modulated optical signal from said output port into an optical fiber.