Virtual local area network memory access system

• US 5,892,922 A
• Filed: 02/28/1997
• Issued: 04/06/1999
• Est. Priority Date: 02/28/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Lorenz, Gary D.
• Primary Examiner(s): Asta, Frank J.
• Assistant Examiner(s): VU, THONG H
• Application Number:
  US08/808,021
• Time in Patent Office: 767 Days
• Field of Search: 375/118, 395/802, 395/425, 395/308, 395/500, 395/335, 395/200.62, 370/249, 370/391, 370/85.13, 370/60, 370/397, 340/172.5, 364/900, 364/200, 179/15, 570/397, 711/167
• US Class Current: 709/238
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof

Abstract

A VLAN memory access system to provide VLAN address table look-ups with the ability to simultaneously do processor read cycles or processor write cycles to the same memory structure with anatomical accesses. The system encompasses the interaction between a memory look-up table that stores the slot allowed transition bit mask for a multi-slot hub based VLAN switch, a switch processor interface that is used to upgrade the memory access table by writing entries into the table or reading the table to verify its contents, and a look-up processor that uses the VLAN table to make forwarding decisions on the destination of a packet based on the value read from the VLAN memory look-up table. The VLAN table accesses must be arbitrated between the look-up processor, which has the highest priority, and read or write accesses from the switch processor. The look-up processor takes the VLAN ID field of a packet and uses this as the address of the slot allowed transmit bit mask to be applied to the destination slot bit mask. This logical AND function is used to determine the final bit mask of slots that will receive this packet.

Claims

1. A virtual local area network (VLAN) memory access system comprising:

a memory lookup table having a read mode and a write mode for reading and writing said memory lookup table for one processing cycle;

a VLAN lookup process for and reading a VLAN ID field of an incoming VLAN packet, said VLAN lookup process using said VLAN ID field as a lookup address in said memory lookup table, said VLAN lookup process reading lookup data from said lookup address, said VLAN lookup process using said lookup data as a VLAN destination address for said VLAN packet;

a switch processor for controlling a switch in a VLAN, said switch processor reading and writing data to said memory lookup table to maintain and monitor said memory lookup table;

first state machine means for giving said VLAN lookup process next access to said mnemory lookup table when an incoming packet needs to be processed, said first state machine giving said switch processor next access to said memory lookup table when no packets need to be processed and said switch processor needs to access said memory lookup table, said first state machine blocking further access to said memory lookup table during said processing cycle when one of said VLAN lookup process and switch processor has access;

a second state machine placing said memory lookup table into said read mode for said processing cycle when one of said VLAN lookup process has accees to said memory lookup table, or said switch processor has access and needs to read said memory lookup table, said second state machine placing said memory lookup table into said write mode for said processing cycle when said switch processor has access to said memory lookup table and needs to write said memory lookup table.

2. A system in accordance with claim 1, wherein:

said VLAN lookup process generates a look-up signal when said VLAN lookup process needs to process said incoming packet;

said switch processor generates a processor request signal when said switch processor needs to read and write to said memory lookup table, said switch processor generates a read signal when said switch processor needs to read from said memory lookup table, said switch processor generates a write signal when said switch processor needs to write to said memory lookup table;

said first state machine includes an idle state, a look-up state, and a processor state, said first state machine going into said idle state when said look-up signal and said processor request signal are not present, said first state machine going into said look-up state when said look-up signal is present, said first state machine going into said processor state when said look-up signal is not present and said processor request signal is present;

a condition A being present when said look-up state is active or (said processor state is active and said read signal is present);

a condition B being present when said processor state is active and said write signal is present;

said second state machine includes an off state, a read state and a write state, said second state machine going into said read state when said condition A is present, said second state machine going into said write state when said condition A is not present and said condition B is present, said second state machine going into said off state when said conditions A and B are not present.

3. A system in accordance with claim 1, wherein:

said memory lookup table includes an address pointer, said address pointer is set equal to said VLAN ID field when said VLAN process has acces to said memory lookup table, said address pointer is set to a switch processor address when said switch procesor has access to said memory lookup table.

4. A system in accordance with claim 2, wherein:

said first and second state machines go into said idle state and into said off state during an undefined condition.

5. A system in accordance with claim 2, wherein:

only one of said idle, look-up and processor states are active at one time, and only one of said off, read and write states are active at one time.

6. A system in accordance with claim 2, further comprising:

a write signal for said memory access lookup table, said write signal being activated when said write state is activated, said write signal being deactivated when one of said off state and said read state are activated.

7. A system in accordance with claim 2, wherein:

when said read state and said look-up state are active, data is read from said memory lookup table to a multicast_-- mask location;

when said read state and said processor state are active, data is read from said memory lookup table to a holding register.

8. A method for accessing memory locations in a VLAN switch, the method comprising:

providing a memory lookup table;

reading a VLAN ID field of an incoming VLAN packet;

using said VLAN ID field as a lookup address in said memory lookup table;

reading lookup data from said lookup address;

using said lookup data as a VLAN destination address for said VLAN packet;

generating a look-up signal when said VLAN lookup process needs to process said incoming packet;

providing a switch processor for controlling the VLAN switch;

said switch processor reading and writing data to said memory lookup table to maintain and monitor said memory lookup table;

said switch processor generating a processor request signal when said switch processor reads and writes to said memory lookup table;

said switch processor generating a read signal when said switch processor needs to read from said memory lookup table;

said switch processor generating a write signal when said switch processor needs to write to said memory lookup table;

activating an idle state when said look-up signal and said processor request signal are not present;

activating a look-up state when said look-up signal is present;

activating a processor state when said look-up signal is not present and said processor request signal is present;

condition A being present when said look-up state is active or (said processor state is active and said read signal is present);

condition B being present when said processor state is active and said write signal is present;

activating a read state when said condition A is present;

activating a write state when said condition A is not present and said condition B is present,

activating an off state when said conditions A and B are not present.

9. A method in accordance with claim 8, wherein:

an address pointer is provided in said memory lookup table;

setting said address pointer equal to said VLAN ID field when said look-up state is active;

setting said address pointer to a switch processor address when said processor state is active.

10. A method in accordance with claim 8, wherein:

activating said idle state and said off state during an undefined condition.

11. A method in accordance with claim 8, wherein:

only one of said idle, look-up and processor states are activated at one time, and only one of said off, read and write states are activated at one time.

12. A method in accordance with claim 8, further comprising:

activating a write signal for said memory access lookup table when said write state is activated;

deactivating said write signal when one of said off state and said read state are activated.

13. A method in accordance with claim 8, wherein:

reading data from said memory lookup table to a multicast_-- mask location when said read state and said look-up state are active;

reading data from said memory lookup table to a holding register when said read state and said processor state are active.

14. A VLAN switch comprising:

a memory lookup table;

VLAN controller means for reading a VLAN ID field of an incoming VLAN packet, said VLAN controller means using said VLAN ID field as a lookup address in said memory lookup table, said VLAN controller means reading lookup data from said lookup address, said VLAN controller means using said lookup data as a VLAN destination address for said VLAN packet, said VLAN controller means generating a look-up signal when said VLAN controller means needs to process said incoming packet;

a switch processor for controlling a switch in a VLAN, said switch processor reading and writing data to said memory lookup table to maintain and monitor said memory lookup table, said switch processor generating a processor request signal when said switch processor reads and writes to said memory lookup table, said switch processor generates a read signal when said switch processor needs to read from said memory lookup table, said switch processor generates a write signal when said switch processor needs to write to said memory lookup table;

a first state machine including an idle state, a look-up state, and a processor state, said first-state machine going into said idle state when said look-up signal and said processor request signal are both not present, said first state machine going into said look-up state when said look-up signal is present, said first-state machine going into said processor state when said look-up signal is not present and said processor request signal is present;

a condition A being present when said look-up state is active or (said processor state is active and said read signal is present);

a condition B being present when said processor state is active and said write signal is present;

a second state machine including an off state, a read state and a write state, said second state machine going into said read state when said condition A is present, said second state machine going into said write state when said condition A is not present and said condition B is present, said second state machine going into said off state when said conditions A and B are not present.

15. A VLAN switch in accordance with claim 14, wherein:

said memory lookup table includes an address pointer, said address pointer is set equal to said VLAN ID field when said first state machine is in said look-up state, said address pointer is set to a switch processor address when said first state machine is in said processor state.

16. A VLAN switch in accordance with claim 14, wherein:

the VLAN memory access system goes into said idle state and into said off state during an undefined condition.

17. A VLAN switch in accordance with claim 14, wherein:

only one of said idle, look-up and processor states are active at one time, and only one of said off, read and write states are active at one time.

18. A VLAN switch in accordance with claim 14, further comprising:

a write signal for said memory access lookup table, said write signal being activated when said write state is activated, said write signal being deactivated when one of said off state and said read state are activated.

19. A VLAN switch in accordance with claim 14, wherein:

when said read state and said look-up state are active, data is read from said memory lookup table to a multicast_-- mask location;

when said read state and said processor state are active, data is read from said memory lookup table to a holding register.