Bus delay compensation circuitry

• US 5,892,927 A
• Filed: 01/08/1997
• Issued: 04/06/1999
• Est. Priority Date: 01/08/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Oliver, D. John, Boehmer, David S.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/780,202
• Time in Patent Office: 818 Days
• Field of Search: 395/280, 395/285, 395/552, 370/519, 370/230, 365/194, 327/276, 327/271, 327/153, 364/431.055
• US Class Current: 710/100
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

Programmable delay compensation for interfacing transceiver with a micro-controller. The total propagation delay in transmitting a symbol across the transceiver and receiving an echo back from the transceiver is programmed by a user or software. Depending upon the protocol used in interfacing and symbol transmission, the total propagation delay, which is stored in a programmable register, is subtracted from prespecified symbol timings so that when the propagation delay is accounted for, the symbols, when echoed, will in reality, match the timings as prespecified by the protocol, so that successive symbols are timed appropriately.

Claims

1. An apparatus for compensating delay in interfacing, using a specified protocol, a transceiver with a micro-controller, said apparatus comprising:

a delay compensation register coupled to said micro-controller, said delay compensation register programmed to store a delay compensation value for said transceiver; and

delay compensation circuitry coupled to said delay compensation register for timing symbols on the micro-controller, said timing to vary from timings of said specified protocol, said variance a function of said delay compensation value.

2. An apparatus for compensating delay according to claim 1 wherein said delay compensation circuitry generates delay compensated output symbols when provided an input data stream.

3. An apparatus for compensating delay according to claim 2 wherein said delay compensation circuitry includes a set of registers, each register storing a nominal timing value according to said specified protocol for a symbol.

4. An apparatus for compensating delay according to claim 3 further comprising a multiplexer coupled to said set of registers, said multiplexer selecting one of said timing values stored in said registers, said selection dependent upon the symbol that said input data stream requires to be transmitted.

5. An apparatus for compensating delay according to claim 4 wherein said delay compensation circuitry includes a subtractor, said subtractor coupled to receive first operand from said delay compensation register, said subtractor further coupled to said multiplexer to receive a second operand from said multiplexer.

6. An apparatus for compensating delay according to claim 5 wherein said subtractor outputs a delay compensated timing which equals said first operand subtracted from said second operand.

7. An apparatus for compensating delay according to claim 6 wherein the delay compensated timing output by said subtractor is coupled to a switch, said switch holding a symbol at a certain logic level for an amount of time determined by said delay compensated timing.

8. A method for compensating delay in interfacing, using a specified protocol, a transceiver with a micro-controller, said transceiver coupled to a bus, said method comprising the steps of:

programming a delay compensation value in propagating symbols generated by the micro-controller through said transceiver; and

adjusting said symbols generated by the micro-controller to match nominal timing values of said protocol after accounting for said compensation value delay.

9. A method for compensating delay according to claim 8 wherein the step of programming comprises the steps of:

programming an amount of delay in propagating a symbol originating from said micro-controller through said transceiver out to said bus; and

programming an amount of delay in propagating an echo of said symbol originating from said micro-controller from said bus through said transceiver back to said micro-controller.

10. A method of compensating delay according to claim 9 wherein said step of programming said delay compensation value comprises the step of adding said amount of delay in propagating a symbol with said amount of delay in propagating an echo.

11. A method according to claim 8 wherein said step of adjusting said symbols includes the step of selecting a nominal timing value from a set of timing values based upon the type of symbol to be generated by said micro-controller.

12. A method of compensating delay according to claim 11 wherein said step of adjusting said symbols further includes the steps of:

subtracting said delay compensation value from said selected nominal timing value to generate a compensated symbol timing; and

outputting a symbol by holding said symbol to its logic level for a duration specified by said compensated symbol timing.

13. A method of compensating delay according to claim 11 wherein said symbols include pulse-width modulated symbols, each of said symbols identified by a fixed nominal timing value.

14. On a bus having nodes, each node having a transceiver, an improved micro-controller coupled to said bus, said micro-controller comprising:

a delay compensation register coupled to said bus, said delay compensation register programmed to store a value corresponding to a delay compensation value for said transceiver, said value received from said bus; and

a delay compensation circuit coupled to said delay compensation register, said delay compensation circuit adjusting the timing of symbols generated by said micro-controller utilizing said delay compensation value.