Field programmable gate array having programming instructions in the configuration bitstream
First Claim
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1. A programmable gate array comprising:
- a bitstream comprising a combination of configuration data and programming instructions;
a processor coupled to the bitstream for separating the configuration data from the programming instructions and for executing the programming instructions and havinga control state machine coupled to receive the configuration bitstream for decoding programming instructions and providing control signals; and
an arithmetic logic unit coupled to receive a control signal from the control state machine and for performing arithmetic functions in response to programming instructions in the bitstream; and
a memory array having a plurality of memory cells for receiving and storing configuration data transmitted from the processor.
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Abstract
A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes the programming instructions to efficiently load configuration data into the configuration memory array. For instance, configuration data can be temporarily stored in the CPU and reused where data patterns in the configuration memory array repeat. Use of the programmable CPU for loading the configuration memory array reduces the amount of data transmitted to the FPGA during array configuration.
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Citations
30 Claims
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1. A programmable gate array comprising:
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a bitstream comprising a combination of configuration data and programming instructions; a processor coupled to the bitstream for separating the configuration data from the programming instructions and for executing the programming instructions and having a control state machine coupled to receive the configuration bitstream for decoding programming instructions and providing control signals; and an arithmetic logic unit coupled to receive a control signal from the control state machine and for performing arithmetic functions in response to programming instructions in the bitstream; and a memory array having a plurality of memory cells for receiving and storing configuration data transmitted from the processor. - View Dependent Claims (2, 3, 4)
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5. A programmable gate array that is programmable with a bitstream having a combination of configuration data and programming instructions, comprising:
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a memory array having a plurality of memory cells for storing configuration data; a frame register coupled to the memory array for receiving configuration data from the bitstream and transferring the configuration data to the memory array; and a processor coupled to the frame register for controlling the transfer of configuration data to the memory array, the processor being responsive to programming instructions in the bitstream and having a control state machine coupled to receive the bitstream for decoding the programming instructions in the bitstream and providing control signals; and an arithmetic logic unit coupled to receive a control signal from the control state machine for performing arithmetic functions in response to the programming instructions in the bitstream. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 30)
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19. An apparatus for configuring the configuration memory array of a field programmable gate array (FPGA) comprising:
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means for encoding gate array configuration data with programming instructions to produce encoded bitstream data; means for transferring bitstream data to the FPGA; means for receiving the bitstream data into a CPU on the FPGA; and means for performing arithmetic functions to configure the FPGA in response to programming instructions in the bitstream. - View Dependent Claims (20, 21, 22)
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23. A method for configuring the configuration memory array of a field programmable gate array (FPGA), the method comprising the steps:
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encoding gate array configuration data with programming instructions to produce encoded bitstream data; transferring bitstream data to the FPGA; receiving the bitstream data into a CPU on the FPGA; decoding the bitstream data to a separate the programming instructions from the configuration data; and performing arithmetic functions to configure the FPGA in response to programming instructions in the bitstream. - View Dependent Claims (24, 25, 26, 27, 28)
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29. A programmable gate array, comprising:
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a processor having an input port for receiving a bitstream, the bitstream having configuration data and programming instructions, the processor for separating the configuration data from the programming instructions and executing the programming instructions, and the processor having a control state machine coupled to receive the configuration bitstream for decoding programming instructions and providing control signals; and an arithmetic logic unit coupled to receive a control signal from the control state machine and for performing arithmetic functions in response to programming instructions in the bitstream; and a memory array having a plurality of memory cells for receiving and storing configuration data transmitted from the processor.
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Specification