Processor complex for executing multimedia functions

• US 5,892,966 A
• Filed: 06/27/1997
• Issued: 04/06/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Patel, Mukesh, Petrick, Bruce E.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/884,257
• Time in Patent Office: 648 Days
• Field of Search: 395/378, 395/800.34, 395/827, 395/800.22, 395/678, 395/814.21, 395/881, 395/737, 395/800.36, 395/800.17, 395/309, 707/206, 707/104, 707/101, 379/93.17, 379/88.13, 348/19, 340/825.47, 364/DIG. 1, 364/DIG. 2
• US Class Current: 712/36
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: Y10S 707/99945 Object-oriented database structure processing
• CPC Class Codes: Y10S 707/99948 Application of database or data structure, e.g. distributed, multimedia, or image

Abstract

A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism. A main memory device is also coupled to the hardware processor over bidirectional port and coupled to the multimedia processor over a second bidirectional port. This arrangement allows the hardware processor and the coprocessor to share main memory and load separate instruction streams from main memory.

Claims

1. A computer processor complex comprising:

a visible register set including registers for a program counter and a data pointer;

a hardware processor operatively coupled to a first bidirectional port on the visible register set;

a multimedia coprocessor operatively coupled to a second bidirectional port on the visible register set; and

a main memory device operatively coupled to the hardware processor over a first bidirectional port and operatively coupled to the multimedia processor over a second bidirectional port, wherein the visible register set facilitates communication between the hardware processor and the multimedia coprocessor.

2. The computer processor complex of claim 1, wherein the hardware processor is a stack based processor.

3. The computer processor complex of claim 1, wherein the hardware processor is a stack based processor compatible with the PicoJava stack based architecture.

4. The computer processor complex of claim 1, wherein the multimedia coprocessor further comprises:

an instruction fetch and decode unit operatively coupled to a plurality of execution units including,

at least one coprocessor integer execution unit operatively coupled to the second bidirectional port on the visible register set,

at least one coprocessor multimedia execution unit having a plurality of integer execution units;

a first register file operatively coupled to the at least one coprocessor multimedia execution unit;

a second register file operatively coupled to the at least one coprocessor integer execution unit;

a memory device operatively coupled to the at least one coprocessor integer execution unit and containing instructions and data for execution on the multimedia coprocessor.

5. The multimedia coprocessor of claim 4 wherein the at least one coprocessor multimedia execution unit includes a superscalar architecture and each of the execution units includes a plurality of pipelined stages.

6. The multimedia coprocessor of claim 4, wherein the at least one coprocessor integer execution unit further comprises an ALU execution unit and a local memory unit, each separately coupled to the instruction fetch and decode unit.

7. The multimedia coprocessor of claim 6, wherein the local memory unit includes a load/store device.

8. The multimedia coprocessor of claim 6, wherein the local memory unit is operatively coupled to the second register file.

9. The multimedia coprocessor of claim 6, wherein the local memory unit is operatively coupled to the first register file.

10. The multimedia coprocessor of claim 4, wherein the at least one coprocessor multimedia execution unit further comprises a first integer execution unit and a second integer execution unit, each separately coupled to the instruction fetch and decode unit.

11. The at least one coprocessor multimedia execution unit of claim 10, wherein the first integer execution unit includes a multiply ALU, and the second ALU includes an adder ALU.

12. A method executed on a computer processor complex, including a hardware processor and a multimedia coprocessor, for processing one or more multimedia instructions, the method comprising the steps of:

determining, using the hardware processor, an instruction location in a main memory device corresponding to the one or more multimedia instructions and a data location in the main memory device corresponding to the one or more data values associated with the one or more multimedia instructions;

storing the instruction location in a program counter register associated with a visible register set;

storing the data location in a data pointer register associated with the visible register set;

loading the multimedia coprocessor with the instruction location stored in the program counter register;

loading the multimedia coprocessor with the data location stored in the data pointer register; and

executing, using the multimedia coprocessor, the one or more multimedia instructions located at the instruction location using data located at the data location stored in the main memory device.

13. The method of claim 12, further including before the determining step, the step of:

executing an instruction stream of one or more non-multimedia instructions on a hardware processor; and

encountering an indicator within the instruction stream, that one or more multimedia instructions are contained within the main memory device.

14. The method of claim 12, further including after the step of storing the data location in a data pointer, the step of:

transmitting a first indication to the multimedia processor indicating that one or more values have been stored in the visible register set; and

transmitting a second indication to the multimedia processor that the multimedia processor should begin processing the multimedia instructions.

15. The method of claim 12, further including after the executing step, the step of:

transmitting an indication to the hardware processor indicating the execution status associated with the multimedia processor.