Processor complex for executing multimedia functions
First Claim
1. A computer processor complex comprising:
- a visible register set including registers for a program counter and a data pointer;
a hardware processor operatively coupled to a first bidirectional port on the visible register set;
a multimedia coprocessor operatively coupled to a second bidirectional port on the visible register set; and
a main memory device operatively coupled to the hardware processor over a first bidirectional port and operatively coupled to the multimedia processor over a second bidirectional port, wherein the visible register set facilitates communication between the hardware processor and the multimedia coprocessor.
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Accused Products
Abstract
A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism. A main memory device is also coupled to the hardware processor over bidirectional port and coupled to the multimedia processor over a second bidirectional port. This arrangement allows the hardware processor and the coprocessor to share main memory and load separate instruction streams from main memory.
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Citations
15 Claims
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1. A computer processor complex comprising:
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a visible register set including registers for a program counter and a data pointer; a hardware processor operatively coupled to a first bidirectional port on the visible register set; a multimedia coprocessor operatively coupled to a second bidirectional port on the visible register set; and a main memory device operatively coupled to the hardware processor over a first bidirectional port and operatively coupled to the multimedia processor over a second bidirectional port, wherein the visible register set facilitates communication between the hardware processor and the multimedia coprocessor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method executed on a computer processor complex, including a hardware processor and a multimedia coprocessor, for processing one or more multimedia instructions, the method comprising the steps of:
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determining, using the hardware processor, an instruction location in a main memory device corresponding to the one or more multimedia instructions and a data location in the main memory device corresponding to the one or more data values associated with the one or more multimedia instructions; storing the instruction location in a program counter register associated with a visible register set; storing the data location in a data pointer register associated with the visible register set; loading the multimedia coprocessor with the instruction location stored in the program counter register; loading the multimedia coprocessor with the data location stored in the data pointer register; and executing, using the multimedia coprocessor, the one or more multimedia instructions located at the instruction location using data located at the data location stored in the main memory device. - View Dependent Claims (13, 14, 15)
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Specification