Baseband phase-locked direct conversion receiver with frequency offset

• US 5,893,029 A
• Filed: 02/10/1997
• Issued: 04/06/1999
• Est. Priority Date: 02/10/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bastani, Babak
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US08/797,144
• Time in Patent Office: 785 Days
• Field of Search: 455/324, 455/313, 455/255-260, 455/264, 455/265, 455/317, 375/329
• US Class Current: 455/321
• CPC Class Codes: H03D 2200/0047 Offset of DC voltage or frequency
• CPC Class Codes: H03D 3/241 the oscillator being part of a phase locked loop
• CPC Class Codes: H03D 5/00 Circuits for demodulating amplitude-modulated or angle-modulated oscillations at will H03D9/00, H03D11/00 take precedence
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

To generate a fixed frequency offset in a direct conversion receiver (200) a phase ramp representing the frequency offset if generated. This phase ramp is combined with the demodulated phase component of a received signal. A phase wrap detection and compensation circuit (224) is capable of detecting and compensating for phase wrap that occur in the phase ramp by differentiating the input and detecting when a phase wrap is about to occur and causes a switch (316) to flip between two conditions. A first condition couples the phase ramp to the output. A second condition compensates when a wrap around has been detected. As such, a VCO (218) produces a local oscillator having a fixed frequency offset that is immune from locking problems that occur when a phase wrap is introduced.

Claims

1. In a baseband receiver having a phase locked loop, a method of phase locking with a frequency offset, comprising:

providing a baseband signal having a phase information portion and an initial frequency offset;

generating a sawtooth signal representing a desired frequency offset;

detecting when the sawtooth signal is at a maximum level; and

compensating for the expected drop in the sawtooth signal in order to generate a phase offset while avoiding loop instability which occur when a ramp has occurred.

2. A baseband receiver, comprising:

a baseband converter;

a local oscillator coupled to the converter having a frequency offset

a baseband demodulator;

a phase locked loop coupled between the baseband demodulator and the baseband converter for stabilizing the frequency offset;

a phase ramp generator coupled to the phase locked loop to introduce a phase offset thereto;

a frequency offset generator to introduce a fixed frequency offset in the phase locked loop;

a compensation circuit coupled to the phase ramp generator to detect and compensate for phase ramp generator deficiencies; and

a loop filter coupled to the output of the compensation circuit.

3. A baseband receiver having a phase locked loop (PLL) capable of locking to a desired frequency to produce a reference signal having a frequency offset, the PLL comprising:

a forward loop, comprising;

an input;

a phase detector;

a ramp generator for generating a ramp signal;

a phase compensation circuit, comprising;

a threshold detector to detect when an abrupt change in the ramp signal has occurred;

a compensator responsive to the threshold detector to neutralize the effects of the abrupt change in the ramp signal when a ramp has occurred;

a loop filter coupled to the output of the phase compensation circuit;

an oscillator coupled to the loop filter which generates the reference signal; and

a feedback loop to feed back the reference signal to the phase detector.

4. The phase locked loop of claim 3, wherein the phase compensation circuit further includes a differentiator coupled to the threshold detector.

5. The phase locked loop of claim 3, wherein the phase compensation circuit further includes a switching block to switch between the ramp signal and a second signal.

6. The phase locked loop of claim 5, wherein the phase compensation circuit further includes a summer which generates the second signal.

7. The phase locked loop of claim 5, wherein the phase compensation circuit further includes a delay circuit coupled to the switching block to make for a smooth switching between the ramp signal and the second signal.

8. The phase locked loop of claim 7, wherein the delay circuit includes an EX-OR gate.