Parallel processing unit with cache memories storing NO-OP mask bits for instructions

• US 5,893,143 A
• Filed: 06/21/1996
• Issued: 04/06/1999
• Est. Priority Date: 06/28/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Nojiri, Tohru, Tanaka, Kazuhiko, Kojima, Keiji, Ishiguro, Masao, Nishioka, Kiyokazu, Fujikawa, Yoshifumi
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/667,670
• Time in Patent Office: 1,019 Days
• Field of Search: 395/391, 395/800.23, 395/800.24, 711/125, 711/120, 711/128, 711/119
• US Class Current: 711/120
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.

Claims

1. A processor comprising:

two or more processing units whose execution sequence is controlled by a sole program counter and are allowed to execute in parallel;

two or more cache memories for storing an instruction to be executed by said processing units, said cache memories corresponding to said processing units, respectively;

a tag memory for storing address information of said instruction stored in said cache memories; and

storage control circuit for storing instruction fields divided from said instruction in the cache memories corresponding to said processing units if the instruction specified by an address indicated by said sole program counter is read from an external memory;

for reading storage information indicating which of said processing units corresponds to the instruction fields divided from said instruction when reading said instruction;

for storing said storage information in said tag memory in association with the corresponding address information for said instruction; and

for controlling storage of each of said instruction fields in the cache memory corresponding to a processing unit which executes each of said instruction fields according to said storage information.