Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control

• US 5,893,153 A
• Filed: 08/02/1996
• Issued: 04/06/1999
• Est. Priority Date: 08/02/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Tzeng, Tzungren A., Normoyle, Kevin
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/691,783
• Time in Patent Office: 977 Days
• Field of Search: 395/468, 395/470, 395/478, 395/860, 395/842, 711/141, 711/143, 711/151
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

An integrated processor includes an on-chip integrated input/output (IO) system (which does not have a on-chip bus) to handle direct memory access (DMA) operations from external IO units and interface with external cache and main memories. The integrated IO system includes an external cache controller that controls access to both the cache and main memory so as to maintain coherency between the cache and main memory. As part of maintaining data coherency, the cache controller prevents race conditions between instructions generated from a core logic unit within the microprocessor and DMA instructions generated from an external IO unit by giving the DMA request priority over the CPU instructions.

Claims

1. A single central processing unit comprising:

a core logic unit; and

an integrated input/output system coupled to said core logic unit and configured to exchange data, without the use of an on bus, with an external memory, an external cache and an external input/output device, said integrated input/output system also configured to prevent a race condition between an instruction from said core logic unit and a direct memory access (DMA) request from said external input/output device that both reference a same memory location by moving said DMA request in front of said instruction and holding said instruction until said DMA request is serviced.

2. The single central processing unit of claim 1 wherein said integrated input/output system comprises:

an external cache controller (ECU), coupled to said core logic unit and configured to exchange data with said external cache;

a memory control unit, directly coupled to said external cache controller and configured to exchange data with said external memory; and

and a bus interface unit, directly coupled to said external cache controller and configured to exchange data with said external input/output device.

3. The single central processing unit of claim 2 wherein said ECU is configured to, in the event of a cache miss, move a DMA request that arrives at said ECU in front of an instruction from said core logic unit that is stored in an ECU queue.

4. The single central processing unit of claim 3 wherein said ECU is configured to move only said DMA request in front of said instruction from said core logic unit when said instruction from said core logic unit is waiting in said ECU queue within said ECU.

5. The single central processing unit of claim 3 wherein said DMA request is moved in front of said instruction when said instruction has requested access to said external memory, but is not yet involved in a line fill operation.

6. The single central processing unit of claim 4 wherein said ECU is further configured to hold said DMA request when an instruction that arrived at said ECU from said core logic unit is in the process of a line fill operation.

7. The single central processing unit of claim 6 wherein said ECU is configured to complete all pending writeback requests to said external cache before said DMA request is executed.

8. The single central processing unit of claim 6 wherein said ECU holds said DMA request by setting a status bit in said ECU queue.

9. The single central processing unit of claim 6 wherein said external cache is a second level cache and wherein said core logic unit further comprises a first level, internal cache.

10. The single central processing unit of claim 9 wherein said ECU further preserves data integrity by writing through data from said first level cache to said second level cache when said first level cache is updated.

11. A computer system that includes the single processing unit of claim 1.

12. A computer system comprising:

a cache memory;

a main memory;

a bus;

at least one input/output device coupled to said external bus; and

a single central processing unit, coupled to said cache memory, to said main memory and to said external bus, said single central processing unit including;

a core logic unit; and

an integrated input/output system coupled to said core logic unit, said integrated input/output system including;

(i) an external cache controller (ECU), coupled to said core logic unit and to said cache, said ECU configured to exchange data with said cache memory;

(ii) an memory control unit, directly coupled to said ECU and to said main memory, said memory control unit configured to exchange data with said main memory; and

(iii) and an external bus interface unit, directly coupled to said ECU without an intervening on-hip bus and coupled to said external bus, said external bus interface unit configured to exchange data with said at least one external input/output device over said external bus;

wherein said integrated input/output system is configured to prevent a race condition between an instruction from said core logic unit and a direct memory access (DMA) request from said external input/output device that both reference a same memory location by moving said DMA request in front of said instruction and holding said instruction until said DMA request is serviced.

13. A method of preventing race conditions in an integrated processor having a central processing unit and an integrated input/output system on a single chip, said method comprising the steps of:

providing a bus interface unit as part of said integrated input/output system to interface to an external bus and to control the exchange of data with external input/output devices;

providing an external cache controller as part of said integrated input/output system to interface to an external cache without the use of an on bus system;

providing a memory controller as part of said integrated input/output system to interface to an external main memory without the use of an on bus system;

simultaneously receiving first and second instructions at said cache controller, said first instruction being an instruction to access memory from said central processing unit and said second instruction being a direct memory access (DMA) instruction from an external input/output device coupled to said bus interface unit; and

implementing a procedural rule to move said DMA instruction in front of said first instruction in execution order thereby preventing a race condition between said first instruction and said DMA instruction, said procedural rule being.

14. The method of claim 13, wherein said procedural rule further include the step of if said first instruction is in a line fill operation, holding said DMA instruction until said line fill operation is completed.

15. The method of claim 14 wherein said fit instruction is held by setting a status bit in a queue in said external cache controller.

16. The method of claim 13 wherein pending writeback requests to said external cache are completed before said DMA instruction is serviced.

17. The method of claim 13 wherein said bus interface unit interfaces with a bus implementing a PCI bus protocol.

18. A single central processing unit comprising:

a core logic unit; and

an integrated input/output system coupled to said core logic unit and configured to exchange data, without the use of an on chip bus, with an external memory, an external cache and an external input/output device, said integrated input/output system also configured to prevent a race condition between an instruction from said core logic unit and a direct memory access (DMA) request from said external input/output device that both reference a same memory location by moving said DMA request in front of said instruction and holding said instruction until said DMA request is serviced, wherein said integrated input/output system is configured to implement a dynamic priority scheme to prevent race conditions.