Method of manufacture of active matrix LED array

• US 5,893,721 A
• Filed: 03/24/1997
• Issued: 04/13/1999
• Est. Priority Date: 03/24/1997
• Status: Expired due to Term

• Current Assignee: Universal Display Corporation
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wright, Phil, Holm, Paige M., Huang, Rong-Ting
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): CHRISTIANSON, KEITH ALAN
• Application Number:
  US08/823,382
• Time in Patent Office: 750 Days
• Field of Search: 438/23, 438/34, 438/35
• US Class Current: 438/34
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A method of fabricating an active matrix LED array includes forming layers of material on a substrate, which layers cooperate to emit light when activated. Row and column dividers are formed in the layers to divide the layers into an array of LEDs arranged in rows and columns. One FET is formed on the row dividers in association with each LED and a source of each FET is connected to an anode of the associated LED. Row and column buses are formed on the row and column dividers, respectively, and the drain of each FET is connected to an adjacent row bus with the gate of each FET being connected to an adjacent column bus. A cathode for each LED is connected as a common terminal for all of the LEDs in the array.

Claims

1. A method of fabricating an active matrix light emitting device array comprising the steps of:

providing a semiconductor substrate having a surface;

forming a plurality of layers of material on the surface of the substrate, the plurality of layers of material cooperating to emit light when activated;

forming row and column dividers in the plurality of layers of material so as to divide the plurality of layers of material into an array of light emitting devices arranged in rows and columns;

forming a plurality of active control circuits on the row dividers one each associated with each light emitting device in the array, each active control circuit including first and second power terminals and a control terminal with the first power terminal of each active control circuit connected to a first terminal of the associated light emitting device, the step including

patterning a plurality of portions of recrystallized amorphous silicon on the row dividers, one each adjacent each light emitting device,

forming a control terminal on each of the plurality of portions of recrystallized amorphous silicon; and

implanting first and second spaced apart power terminals in each of the plurality of portions of recrystallized amorphous silicon, using the control terminals as a self-aligned mask;

forming row and column buses on the row and column dividers, respectively, and coupling the second power terminal in each active control circuit to an adjacent row bus and the control terminal in each active control circuit to an adjacent column bus; and

forming a second terminal for each light emitting device in the array as a common terminal for all of the light emitting devices in the array.

2. A method of fabricating an active matrix light emitting device array as claimed in claim 1 wherein the step of providing the semiconductor substrate includes providing a substrate of one of GaAs, SiC, semi-insulating GaAs, and Sapphire.

3. A method of fabricating an active matrix light emitting device array as claimed in claim 1 wherein the step of forming the plurality of layers of material includes epitaxially growing layers of semiconductor material on the surface.

4. A method of fabricating an active matrix light emitting device array as claimed in claim 1 wherein the step of forming the plurality of layers of material includes depositing layers of organic material.

5. A method of fabricating an active matrix light emitting device array as claimed in claim 3 wherein the step of forming row and column dividers in the plurality of layers includes implanting material to increase the resistance and isolate the light emitting devices from each other.

6. A method of fabricating an active matrix light emitting device array as claimed in claim 5 wherein the step of implanting material to increase the resistance and isolate the light emitting devices includes implanting one of oxygen and hydrogen ions in semiconductor layers of material.

7. A method of fabricating an active matrix light emitting device array as claimed in claim 1 wherein the step of forming the control terminals includes forming the column buses.

8. A method of fabricating an active matrix light emitting device array as claimed in claim 1 wherein the step of forming the control terminal on each of the plurality of portions of recrystallized amorphous silicon includes depositing a layer of gate dielectric on each of the plurality of portions of recrystallized amorphous silicon and depositing gate material on each of the layers of gate dielectric between the spaced apart power terminals.

9. A method of fabricating an active matrix light emitting device array as claimed in claim 1 wherein the step of forming the second terminal for each light emitting device includes forming an ohmic metal contact on a reverse side of the substrate.

10. A method of fabricating an active matrix light emitting device array comprising the steps of:

providing a semiconductor substrate having a surface;

epitaxially growing a plurality of layers of semiconductor material on the surface of the substrate, the plurality of layers of semiconductor material cooperating to emit light when activated;

implanting row and column isolating dividers in the plurality of layers of material so as to divide the plurality of layers of material into an array of light emitting devices arranged in rows and columns;

patterning a plurality of portions of recrystallized amorphous silicon on the row dividers, one each adjacent each light emitting device;

forming a control terminal on each of the plurality of portions of recrystallized amorphous silicon and forming a plurality of row buses connecting the control terminals into rows;

implanting first and second spaced apart power terminals in each of the plurality of portions of recrystallized amorphous silicon, using the control terminals as a self-aligned mask to define a plurality of field effect transistors;

connecting a first power terminal of each of the field effect transistors to a first terminal of the associated light emitting device;

forming a plurality of column buses connecting the second power terminal of each of the plurality of field effect transistors into columns; and

forming a second terminal for each light emitting device in the array as a common terminal for all of the light emitting devices in the array.

11. A method of fabricating an active matrix light emitting device array as claimed in claim 10 wherein the step of implanting row and column isolating dividers includes implanting one of oxygen and hydrogen ions in the plurality of layers of semiconductor material.

12. A method of fabricating an active matrix light emitting device array as claimed in claim 10 wherein the step of forming the control terminal on each of the plurality of portions of recrystallized amorphous silicon includes depositing a layer of gate dielectric on each of the plurality of portions of recrystallized amorphous silicon and depositing gate material on each of the layers of gate dielectric between the spaced apart power terminals.

13. A method of fabricating an active matrix light emitting device array as claimed in claim 10 wherein the step of forming the second terminal for each light emitting device includes forming an ohmic metal contact on a reverse side of the substrate.

14. A method of fabricating a plurality of layers of semiconductor devices and circuits on a substrate comprising the steps of:

providing a substrate having a surface;

positioning a plurality of layers of material on the surface of the substrate and forming semiconductor devices in the layers of material; and

forming a plurality of circuits on the layers of material including the steps of

patterning recrystallized amorphous silicon on the plurality of layers of material,

forming terminals in the recrystallized amorphous silicon in communication with the semiconductor devices, and

forming the plurality of circuits in communication with the terminals in the recrystallized amorphous silicon.

15. A method of fabricating a plurality of layers of semiconductor devices and circuits on a substrate as claimed in claim 14 wherein the step of providing the substrate includes providing a semiconductor substrate.

16. A method of fabricating a plurality of layers of semiconductor devices and circuits on a substrate as claimed in claim 15 wherein the step of providing the semiconductor substrate includes providing a substrate of one of GaAs, SiC, semi-insulating GaAs, and Sapphire.

17. A method of fabricating a plurality of layers of semiconductor devices and circuits on a substrate as claimed in claim 15 wherein the step of positioning the plurality of layers of material includes epitaxially growing layers of semiconductor material on the surface.