MOS transistor having an offset resistance derived from a multiple region gate electrode
First Claim
1. A metal oxide semiconductor transistor, comprising:
- a channel region;
a gate insulation layer formed on said channel region;
a gate electrode formed on said gate insulation layer;
a source region formed adjacent a first side of said channel region and being self-aligned with said channel region;
a drain region formed adjacent a second side of said channel region opposite said first side and being self-aligned with said channel region;
said gate electrode comprising;
a central conductor region of a first conductivity type formed in a center of said gate electrode,a first adjacent conductor region of a second conductivity type formed adjacent a first side of said central conductor region,a second adjacent conductor region of said second conductivity type formed adjacent a second side of said central conductor region opposite said first side, said first and second adjacent conductor regions of said gate electrode forming first and second junctions with said central conductor region, respectively, andbiasing means for forward biasing said first and second junctions when a turn-on voltage is applied to said central conductor region, and for reverse biasing said first and second junctions when a turn-off voltage is applied to said central conductor region.
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Accused Products
Abstract
A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions. If a gate turn-off voltage is applied to the central region the central region becomes reverse biased with the left and right adjacent regions and thus the effective length of the gate electrode becomes the length of only the central region of the first conductivity type. This reduces the length of the channel region, and thus forms an offset resistance structure which reduces leakage current in the off state of the MOS transistor.
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Citations
18 Claims
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1. A metal oxide semiconductor transistor, comprising:
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a channel region; a gate insulation layer formed on said channel region; a gate electrode formed on said gate insulation layer; a source region formed adjacent a first side of said channel region and being self-aligned with said channel region; a drain region formed adjacent a second side of said channel region opposite said first side and being self-aligned with said channel region; said gate electrode comprising; a central conductor region of a first conductivity type formed in a center of said gate electrode, a first adjacent conductor region of a second conductivity type formed adjacent a first side of said central conductor region, a second adjacent conductor region of said second conductivity type formed adjacent a second side of said central conductor region opposite said first side, said first and second adjacent conductor regions of said gate electrode forming first and second junctions with said central conductor region, respectively, and biasing means for forward biasing said first and second junctions when a turn-on voltage is applied to said central conductor region, and for reverse biasing said first and second junctions when a turn-off voltage is applied to said central conductor region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 14, 15, 16, 17, 18)
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8. A metal oxide semiconductor transistor, comprising:
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a channel region; a gate insulation layer formed on said channel region; a gate electrode formed on said gate insulation layer, said gate electrode comprising; a central semiconductor region of a first conductivity type formed in a center of said gate electrode, a first adjacent semiconductor region of a second conductivity type formed adjacent a first side of said central semiconductor region, a second adjacent semiconductor region of said second conductivity type formed adjacent a second side of said central semiconductor region opposite said first side, said first and second adjacent semiconductor regions of said gate electrode forming first and second junctions with said central semiconductor region, respectively, a third adjacent semiconductor region of said first conductivity type formed adjacent a first side of said first adjacent semiconductor region opposite said first junction, and a fourth adjacent semiconductor region of said first conductivity type formed adjacent a first side of said second semiconductor region opposite said second junction, said third and fourth adjacent semiconductor regions of said gate electrode forming third and fourth junctions with said first and second adjacent semiconductor regions of said gate electrode, respectively; a source region formed adjacent a first side channel region and being self-aligned with said channel region; and a drain region formed adjacent a second side of said channel region opposite said first side and being self-aligned with said channel region. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification