MOS transistor having an offset resistance derived from a multiple region gate electrode

• US 5,894,157 A
• Filed: 06/27/1994
• Issued: 04/13/1999
• Est. Priority Date: 06/25/1993
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Min, Byung-Hyuk, Han, Min-Koo
• Primary Examiner(s): Crane, Sara W.
• Application Number:
  US08/266,420
• Time in Patent Office: 1,751 Days
• Field of Search: 257/66, 257/75, 257/270, 257/364-367, 257/412, 257/407, 257/28
• US Class Current: 257/407
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions. If a gate turn-off voltage is applied to the central region the central region becomes reverse biased with the left and right adjacent regions and thus the effective length of the gate electrode becomes the length of only the central region of the first conductivity type. This reduces the length of the channel region, and thus forms an offset resistance structure which reduces leakage current in the off state of the MOS transistor.

Claims

1. A metal oxide semiconductor transistor, comprising:

a channel region;

a gate insulation layer formed on said channel region;

a gate electrode formed on said gate insulation layer;

a source region formed adjacent a first side of said channel region and being self-aligned with said channel region;

a drain region formed adjacent a second side of said channel region opposite said first side and being self-aligned with said channel region;

said gate electrode comprising;

a central conductor region of a first conductivity type formed in a center of said gate electrode,

a first adjacent conductor region of a second conductivity type formed adjacent a first side of said central conductor region,

a second adjacent conductor region of said second conductivity type formed adjacent a second side of said central conductor region opposite said first side, said first and second adjacent conductor regions of said gate electrode forming first and second junctions with said central conductor region, respectively, and

biasing means for forward biasing said first and second junctions when a turn-on voltage is applied to said central conductor region, and for reverse biasing said first and second junctions when a turn-off voltage is applied to said central conductor region.

2. A metal oxide semiconductor transistor according to claim 1, wherein said channel region is formed of polycrystalline silicon.

3. A metal oxide semiconductor transistor according to claim 1, wherein said channel region is formed of amorphous silicon.

4. A metal oxide semiconductor transistor according to claim 1, wherein said channel region is formed of single crystalline silicon.

5. A metal oxide semiconductor transistor according to claim 1 wherein said first conductivity type is opposite said second conductivity type.

6. A metal oxide semiconductor transistor according to claim 5 wherein said first conductivity type is a P-type semiconductor material and said second conductivity type is an N-type semiconductor material.

7. A metal oxide semiconductor according to claim 1 wherein said central conductor region, said first adjacent conductor region and said second adjacent conductor region are coplanar.

14. A metal oxide semiconductor according to claim 1, wherein said gate electrode further comprises:

a third adjacent semiconductor region of said first conductivity type formed adjacent a first side of said first adjacent semiconductor region opposite said first junction, and

a fourth adjacent semiconductor region of said first conductivity type formed adjacent a first side of said second semiconductor region opposite said second junction, said third and fourth adjacent semiconductor regions of said gate electrode forming third and fourth junctions with said first and second adjacent semiconductor regions of said gate electrode, respectively.

15. A metal oxide semiconductor according to claim 14, wherein said biasing means includes means for applying a predetermined voltage to said third and fourth adjacent semiconductor regions of said gate electrode.

16. A metal oxide semiconductor according to claim 15, wherein said predetermined voltage has a level between said turn-off voltage and said turn-on voltage.

17. A metal oxide semiconductor according to claim 14, wherein said biasing means includes means for connecting said third adjacent semiconductor region to one of said source and drain regions and means for connecting said fourth adjacent semiconductor region to the other of said source and drain regions.

18. A metal oxide semiconductor according to claim 14, wherein said biasing means includes means for commonly connecting said third and fourth adjacent semiconductor regions to one of said source and drain regions.

8. A metal oxide semiconductor transistor, comprising:

a channel region;

a gate insulation layer formed on said channel region;

a gate electrode formed on said gate insulation layer, said gate electrode comprising;

a central semiconductor region of a first conductivity type formed in a center of said gate electrode,

a first adjacent semiconductor region of a second conductivity type formed adjacent a first side of said central semiconductor region,

a second adjacent semiconductor region of said second conductivity type formed adjacent a second side of said central semiconductor region opposite said first side, said first and second adjacent semiconductor regions of said gate electrode forming first and second junctions with said central semiconductor region, respectively,

a third adjacent semiconductor region of said first conductivity type formed adjacent a first side of said first adjacent semiconductor region opposite said first junction, and

a fourth adjacent semiconductor region of said first conductivity type formed adjacent a first side of said second semiconductor region opposite said second junction, said third and fourth adjacent semiconductor regions of said gate electrode forming third and fourth junctions with said first and second adjacent semiconductor regions of said gate electrode, respectively;

a source region formed adjacent a first side channel region and being self-aligned with said channel region; and

a drain region formed adjacent a second side of said channel region opposite said first side and being self-aligned with said channel region.

9. A metal oxide semiconductor transistor according to claim 8, wherein said third and fourth adjacent conductor regions are connected to a predetermined voltage source which provides a voltage which is less than a maximum voltage to be applied to said central conductor region of said gate electrode.

10. A metal oxide semiconductor transistor according to claim 8, wherein said third adjacent, said first adjacent, said central, said second adjacent, and said fourth adjacent semiconductor regions of said gate electrode form respectively a PNPNP junction over said channel region.

11. A metal oxide semiconductor transistor according to claim 8, wherein said third adjacent, said first adjacent, said central, said second adjacent, and said fourth adjacent semiconductor regions of said gate electrode form respectively an NPNPN junction over said channel region.

12. A metal oxide semiconductor transistor according to claim 8, wherein said metal oxide semiconductor transistor is a thin film MOS transistor.

13. A metal oxide semiconductor transistor according to claim 8, wherein said first conductivity type is a P-type semiconductor material and said second conductivity type is an N-type semiconductor material.