Single shot with pulse width controlled by reference oscillator

• US 5,894,239 A
• Filed: 04/18/1997
• Issued: 04/13/1999
• Est. Priority Date: 04/18/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lang, Kirk W., Bonaccio, Anthony R.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/844,082
• Time in Patent Office: 725 Days
• Field of Search: 327/172-176, 327/156, 327/157, 327/159, 327/227, 327/230, 375/374-376, 331/1 A, 331/17, 331/25
• US Class Current: 327/176
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A one-shot structure for controlling pulse widths on integrated circuit chips by using a reference oscillator to compensate the rate at which a capacitor is discharged through a transistor in a reference pulse generator. Compensation is accomplished by using a feedback circuit to control the voltage applied to the transistor in the reference pulse generator. The reference oscillator is used with the reference pulse generator to generate a control voltage which matches the reference pulse to the reference oscillator. The same control voltage is then applied to a desired pulse generator. The desired pulse generator has the same one-shot structure as the reference pulse generator, namely a capacitor and a discharge transistor. The pulse width of the desired pulse generator is determined by scaling the geometry of the capacitor and the discharge transistor in the desired pulse generator relative to the geometry of the corresponding components in the reference pulse generator. These relative geometries remain consistent within relatively small tolerances for a chip in a typical integrated circuit process, compared to relatively large variances between design values and absolute chip geometries.

Claims

1. A circuit for generating an output signal having a single-shot pulse with a desired time duration, said duration controlled by a reference oscillator signal, said reference oscillator signal having a pulse width and a period, comprising:

a reference signal said reference signal having a pulse width;

means for matching said reference signal pulse width to said reference oscillator signal pulse width; and

means for generating said output signal having a single-shot pulse whose width is related to the pulse width of said reference signal by a fixed factor, said output signal being triggered by an output signal,

wherein said input signal has no pulse width, phase or frequency relationship to said reference oscillator signal.

2. The circuit of claim 1, wherein said matching means comprises:

means for triggering said reference signal with said reference oscillator signal;

means for comparing said reference signal to said reference oscillator signal; and

means for changing a control voltage if said pulse width of said reference signal is different from said pulse width of said reference oscillator signal, wherein said pulse width of said reference signal is differentially controlled by said control voltage.

3. The circuit of claim 2, wherein the pulse width of the reference signal and the pulse width of the output signal are created in an integrated circuit by respective one-shot structures, said one-shot structures having relative physical geometries on said integrated circuit which establish said fixed factor, said one-shot structures both being controlled by said control voltage.

4. The circuit of claim 3, wherein said comparing means comprises:

first comparator means for signaling when said reference oscillator signal falls before said reference signal; and

second comparator means for signaling when said reference oscillator signal falls after said reference signal.

5. The circuit of claim 4, wherein said control voltage changing means comprises:

means for charging a control capacitor responsive to said signaling from said first comparator means; and

means for discharging said control capacitor responsive to said signaling from said second comparator means, wherein said control voltage is driven by a charge on said control capacitor.

6. The circuit of claim 1, wherein said matching comprises:

means for generating said reference signal pulse width, responsive to said reference oscillator signal pulse width; and

means for generating a control voltage, responsive to said reference oscillator signal pulse width and said reference signal pulse width, wherein said reference signal pulse width is differentially controlled by said control voltage.

7. The circuit of claim 3, wherein each said one-shot structure comprises:

means for charging a capacitor when a triggering signal is less than a first threshold value;

means for discharging said capacitor responsive to a rising edge of said triggering signal, said discharge being at a rate controlled by said control voltage, wherein a voltage across said capacitor is measured at a charge node; and

means for gating said triggering signal and said charge node voltage to produce said single-shot pulse, said single shot pulse rising when said triggering signal is higher than a second threshold value and falling when said charge node voltage falls below a switch point of said gating means, wherein said triggering signal for said reference signal generating one-shot structure is said reference oscillator signal and said triggering signal for said one-shot structure generating the output signal is said input signal.

8. The circuit of claim 7, wherein said charging means comprises:

a PFET whose source is connected to a supply voltage, whose drain is connected to said charge node and whose gate is driven by said triggering signal; and

a capacitor connected between said charge node and ground;

and wherein said discharging means comprises;

an NFET whose source is connected to ground, whose drain is connected to said charge node, and whose gate is driven by said control voltage;

and wherein said gating means is an AND gate.

9. The circuit of claim 8, wherein said triggering means comprises:

a delay gate for delaying said reference oscillator signal, said delay gate having an input and an output;

an OR gate having first and second inputs and an output, said first input being said reference oscillator signal and said second input being said output of said delay gate;

wherein said output of said OR gate is an input to said AND gate.

10. The circuit of claim 3, wherein said comparing means comprises a charge pump for generating said control voltage.

11. The circuit of claim 10, wherein said charge pump comprises:

a gate for inverting said reference pulse;

an UP gate and a DOWN gate, respectively, each having an output and each having said reference oscillator signal and said inverted reference pulse as inputs, said UP gate output being low when said inputs are both low and being high otherwise, said DOWN gate output being high when said inputs are both high and being low otherwise;

an UP gate switch and a DOWN gate switch, said UP gate switch charging a control capacitor when said UP gate output is low and being off otherwise and said DOWN gate switch discharging said control capacitor when said DOWN gate output is high and being off otherwise;

wherein said control voltage is responsive to the charge on said control capacitor.

12. The circuit of claim 11, wherein said UP gate is an OR gate, said DOWN gate is an AND gate, said UP gate switch is a PFET having a gate, a source, and a drain, and said DOWN gate switch is an NFET having a gate, a source, and a drain, said UP gate output being connected to said PFET gate, said DOWN gate output being connected to said NFET gate, said PFET source being connected to said supply voltage, said NFET source being connected to said ground, said PFET drain being connected to said NFET drain at a node of said control voltage, and said control capacitor being connected between said node of said control voltage and said ground.