Common-mode output sensing circuit
First Claim
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1. An integrated circuit, comprising:
- an amplifier having a first input coupled for receiving an input signal and having a first output for providing an output signal;
a first switched capacitor circuit having a first control input responsive to a first clock signal for coupling the first switched capacitor circuit to a first reference conductor during a first time period, and a second control input responsive to a second clock signal for coupling the first switched capacitor circuit to the first output of the amplifier during a second time period; and
a second switched capacitor circuit having a first control input responsive to the second clock signal for coupling the second switched capacitor circuit to the first reference conductor during the second time period, and a second control input responsive to the first clock signal for coupling the second switched capacitor circuit to the first output during the first time period.
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Abstract
A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (VAGO) during a second clock phase, which increases the output loading during the second clock phase (P2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P1) to match the load produced by the refresh circuit (604) during the second clock phase (P2).
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Citations
21 Claims
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1. An integrated circuit, comprising:
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an amplifier having a first input coupled for receiving an input signal and having a first output for providing an output signal; a first switched capacitor circuit having a first control input responsive to a first clock signal for coupling the first switched capacitor circuit to a first reference conductor during a first time period, and a second control input responsive to a second clock signal for coupling the first switched capacitor circuit to the first output of the amplifier during a second time period; and a second switched capacitor circuit having a first control input responsive to the second clock signal for coupling the second switched capacitor circuit to the first reference conductor during the second time period, and a second control input responsive to the first clock signal for coupling the second switched capacitor circuit to the first output during the first time period. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated analog to digital converter (ADC), comprising:
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a first comparator having first and second inputs coupled for comparing an analog input signal to a reference voltage to produce a first digital data bit; a first ADC stage having a first input coupled for sampling the analog input signal during a first time period and producing a first residue signal at an output during a second time period, the first ADC stage including, (1) a first amplifier having a first input coupled for receiving the analog input signal and a first output for providing the first residue signal; (2) a first switched capacitor circuit having a first control input responsive to a first clock signal for coupling the first switched capacitor circuit to a first reference conductor during the first time period, and a second control input responsive to a second clock signal for coupling the first switched capacitor circuit to the first output of the first amplifier during the second time period; and (3) a second switched capacitor circuit having a first control input responsive to the second clock signal for coupling the second switched capacitor circuit to the first reference conductor during the second time period, and a second control input responsive to the first clock signal for coupling the second switched capacitor circuit to the first output of the first amplifier during the first time period. - View Dependent Claims (8, 9, 10, 11)
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12. A wireless communication device, comprising:
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a receiver circuit having an input coupled for receiving a radio frequency carrier signal and an output for providing an analog carrier signal; an analog-to-digital converter (ADC), including, (1) a first differential amplifier having a differential input for sampling the analog carrier signal during a first clock phase; (2) a first switched capacitor circuit having first and second control inputs for respectively coupling the first switched capacitor circuit across first and second common-mode reference conductors during a second clock phase, and across a differential output of the first differential amplifier during the first clock phase; (3) a second switched capacitor circuit having first and second control inputs for respectively coupling the second switched capacitor circuit across the first and second common-mode reference conductors during the first clock phase, and across the differential output of the first differential amplifier during the first clock phase; (4) a first comparator having an input for receiving the analog carrier signal and providing a first data word during the second clock phase to an output of the ADC; (5) a second differential amplifier having a differential input for sampling the analog carrier signal during the second clock phase; (6) a third switched capacitor circuit having first and second control inputs for respectively coupling the third switched capacitor circuit across the first and second common-mode reference conductors during the first clock phase, and across a differential output of the second differential amplifier during the second clock phase; (7) a fourth switched capacitor circuit having first and second control inputs for respectively coupling the fourth switched capacitor circuit across the first and second common-mode reference conductors during the second clock phase, and across the differential output of the second differential amplifier during the first clock phase; (8) a second comparator having an input for receiving the analog carrier signal and providing a second data word to the output of the ADC during the first clock phase; and a demodulator having an input coupled to the output of the ADC and an output for providing a demodulated signal. - View Dependent Claims (13)
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14. A method of refreshing a common-mode voltage at a first output of an amplifier circuit, comprising the steps of:
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precharging a first capacitance to a desired common-mode voltage during a first clock phase; discharging the first capacitance at the first output during a second clock phase; precharging a second capacitance to the desired common-mode voltage during a second clock phase; and discharging the second capacitance at the first output during the first clock phase. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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Specification