Image processing apparatus for processing digital signals

• US 5,894,312 A
• Filed: 05/05/1997
• Issued: 04/13/1999
• Est. Priority Date: 05/08/1996
• Status: Expired due to Fees

• Current Assignee: Fuji Xerox Company Limited (Fujifilm Holdings Corporation)
• Original Assignee: Fuji Xerox Company Limited (Fujifilm Holdings Corporation)
• Inventors: Suda, Takeshi, Ishiwata, Masahiro
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/851,031
• Time in Patent Office: 708 Days
• Field of Search: 345/501-504, 345/507-509, 345/521, 345/526, 345/418, 345/473, 711/5, 711/100
• US Class Current: 345/504
• CPC Class Codes: G06T 1/60 Memory management

Abstract

An image processing apparatus is disclosed which is connected to external machines for inputting data therefrom to a plurality of image memories and outputting data from the plurality of image memories thereto. The image processing apparatus includes a plurality of memory access controllers connected to the plurality of image memories, and a control device for selecting, a first mode for the plurality of memory access controllers to access the image memories separately, or a second mode for a master controller, which is one of the memory access controllers, to access the plurality of image memories as one image memory space so a to control the plurality of memory access controllers.

Claims

1. An image processing apparatus connected to external machines for inputting data therefrom to a plurality of image memories and outputting data from said plurality of image memories thereto comprising:

a plurality of memory access controllers connected to said plurality of image memories;

control means for selecting;

a first mode for said plurality of memory access controllers to access said image memories separately;

or a second mode for a master controller, which is one of said memory access controllers, to access said plurality of image memories as one image memory space so as to control said plurality of memory access

an area signal generator for outputting an area signal indicating that data on a data bus is valid based on a control signal input from the external machine.

2. The image processing apparatus of claim 1, wherein

in the second mode, said master controller outputs a control signal to a slave controller, which is a memory access controller other than said master controller, for prohibiting said slave controller from accessing said image memory.

3. The image processing apparatus of claim 2, wherein

said master controller and said slave controller adopt the same architecture.

4. The image processing apparatus of claim 1, further comprising:

data selectors provided in a one-to-one correspondence with the external machines for controlling data input/output,

wherein said memory access controllers operate based on the area signal output from said signal generator.

5. The image processing apparatus of claim 4, further comprising:

data bus controllers for controlling data input/output from/to said data selector and said image memory access controllers.

6. The image processing apparatus of claim 5, wherein

as many data bus controllers as the number of connected external machines or the number of said image memories, whichever is the greater, are provided.

7. The image processing apparatus of claim 5, wherein

said data bus controller is capable to output data input from said one external machine to said plurality of memory access controllers.

8. The image processing apparatus of claim 5, wherein

said data bus controller is capable to transfer data from said memory access controller to one or more different memory access controllers.

9. The image processing apparatus of claim 5, wherein

said control means controls sections based on instructions from a host computer, and said data bus controller also controls data input/output from/to said host computer.

10. The image processing apparatus of claim 5, wherein

said data bus controller inputs/outputs a predetermined invalid data value in a period in which data on said data bus is invalid.

11. The image processing apparatus of claim 4, wherein

said memory access controller executes address conversion based on the area signal output from said area signal generator and given access position information, and reads/writes data from/into said image memory.

12. The image processing apparatus of claim 11, wherein

said memory access controller executes image conversion processing by the address conversion.

13. The image processing apparatus of claim 4, wherein

said data selector is capable to select any data read from said plurality of image memories, and wherein said several data selectors select data read from one image memory for outputting to said external machines.

14. The image processing apparatus of claim 4, wherein

said memory access controller has a mode for accessing said image memory in synchronization with a new synchronizing signal even if the area signal output from said area signal generator is invalid.

15. The image processing apparatus of claim 4, wherein

said memory access controller has a fast page access mode as well as a normal access mode.

16. The image processing apparatus of claim 4, wherein

said memory access controller contains an FIFO, and is capable to set a write timing of data into said FIFO.