Fiber channel switch employing distributed queuing

• US 5,894,481 A
• Filed: 09/11/1996
• Issued: 04/13/1999
• Est. Priority Date: 09/11/1996
• Status: Expired due to Fees

• Current Assignee: Mcdata Corporation (Broadcom, Inc.)
• Original Assignee: Mcdata Corporation (Broadcom, Inc.)
• Inventors: Book, David
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): HOM, SHICK C
• Application Number:
  US08/714,029
• Time in Patent Office: 944 Days
• Field of Search: 370/412, 370/396, 370/395, 370/394, 370/360, 370/236, 370/398, 359/139, 359/140, 359/118, 395/872, 395/874
• US Class Current: 370/412
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/608 ATM switches adapted to switch variable length packets, e.g. IP packets
• CPC Class Codes: H04Q 11/0421 Circuit arrangements therefor

Abstract

The present invention is a fiber channel switch employing a distributed queuing algorithm for interconnecting a plurality of devices (workstations, supercomputer, peripherals) through their associated node ports (N_-- ports) and employs a fabric having a shared memory coupled to a plurality of fabric ports (F_-- ports) through a bi-directional bus over which memory addresses, frame data and communications commands are transmitted. Each F_-- port includes a port controller employing a distributed queuing algorithm associated with a control network for communicating commands between the ports related to when and where frame transfers should be made, wherein the bi-directional bus provides an independent data network for access to the shared memory such that frames can be transferred to and from the shared memory in response to port controller commands.

Claims

1. A fibre channel switch for interconnecting a plurality of devices, each device having a node port, such that frames of data originating from a source port having a source node port may be transferred through the fibre channel switch to a destination device having a destination node port in accordance with a distributed source and destination queuing algorithm, comprising:

a plurality of fabric ports, each fabric port coupled to a different device through corresponding source or destination node port,

a plurality of port controllers, each port controller located on a different fabric port, each port controller further comprising the distributed source and destination queuing algorithm for queuing frames sourced or destined from a device, or to, itself, and wherein, each port controller operates independently of the queuing of frames by any other port controller,

a control network for communicating timing and destination commands between each port controller corresponding to when and where frame transfers are to be made,

a bit-sliced shared memory having a common pool of memory buffers,

a shared memory controller coupled to each port controller, for bit-slicing data and memory addresses being transmitted between the port controllers and the shared memory, wherein data and destination addresses are transferred to and from the shared memory, the bit-sliced shared memory being coupled to each fabric port through the shared memory controller, wherein each fabric port can access the shared memory directly.

2. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 1, the bit-sliced shared memory being bit-sliced to degree n, and the common pool of memory buffers is constructed from n blocks, each with a memory bandwidth mb, given by:

mb=(2×

b×

p)/n, where b is equal to the data bandwidth of a single fabric port, p is equal to the number of fabric ports and n represents the degree of bit-slicing.

3. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 2, wherein, each port delivers and receives 1 bit of data at a time to, and from, each memory bank, and over 2p clock cycles these bits are accumulated, and wherein, every fabric port has access to the shared memory.

4. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 1, each port controller further comprising a writer and a reader, each writer further containing a separate destination queue for each destination port, wherein each source port passes the buffer descriptor at the head of its destination queues to the destination port before the source port is actually ready to forward the frame such that each destination port knows about the next frame that each of the source ports wants to forward next.

5. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 4, wherein upon forwarding a frame from a particular source port to a device, the destination port requests the next buffer descriptor in the source port queue, and wherein, depending on the latency of the request and response between the two port controllers and the length of the frame being transmitted, the destination port will get the next buffer descriptor before or at approximately the same time transmission of the current frame completes, and wherein, by overlapping these two operations, a very high rate of sustained bandwidth can be maintained between two ports sending frames back and forth to each other.

6. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 2, wherein p=18 fabric ports and b=800 Mbits/sec, n=36 memory devices and mb=800 Mbits/sec, and wherein, the tx side of all ports retrieve data directly from the same memory which the rx side accesses.

7. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 1, each port controller further comprising:

a link controller for controlling the link between the node port and the fabric port,

a frame transfer controller for receiving and transmitting data between the link controller and the shared memory,

an address validation/translation controller for obtaining frame header information and for generating destination port numbers, buffer numbers, and timeout values,

a synchronizer for synchronizing port state transitions and the activities of the reader and writer, a statistics controller for counting statistics, and

a port communications controller for enabling port controllers to communicate.

8. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 7, the address validation/translation controller further comprising:

a timer for timing and timeout handling of frames in the queue, such that upon passing a buffer descriptor to the destination fabric port, the port controller from the source fabric port remembers the frame.

9. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 8, wherein the port controller, in response to the timer, sends a busy frame signal back to the source node port, or discards the frame, if the frame cannot be forwarded out to the destination fabric Port within a fixed time period.

10. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 9, wherein the fixed time period is determined in accordance with the Fibre channel standard.

11. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 10, wherein the source fabric port retains responsibility for timing the frame until the source fabric port buffer descriptor makes it to the head of the source queue and is passed to the destination queue, such that the destination port may now forward a request to the source fabric port to return a busy frame signal.

12. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 9, further comprising the step of link resetting the source fabric port and discarding the contents of the buffer, and wherein, the source fabric port stops the destination fabric port from forwarding the frame.

13. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 2, the plurality of port controllers further comprising a "non-core function port" port controller, wherein, the buffer descriptor of the frame to be busied or rejected is queued to the "non-core function port" port controller, wherein the source fabric port is not required to generate busy and reject frame commands.

14. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 13, the "non-core function port" port controller further comprising software for manipulation of the frame header, and further comprising the step of queuing the frame back out to the original source fabric port, and wherein, the source fabric port continues to time the frame while the original frame is queued to the "non-core function port", and wherein, if the frame is not forwarded within a predetermined period of time, the source fabric port makes a request to the "non-core function port" port controller not to forward the original frame to the processor, and wherein, if the frame does make it the processor, and the reject/busy frame is queued back to the source fabric port, the "non-core function port" port controller must time the frame and discard it if necessary.

15. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 14, further comprising a "non-core function port" timer that times the time between when the frame was first queued to the "non-core function" port and when it was actually delivered to it.

16. The fibre channel switch employing the distributed source and destination queuing algorithm as claimed in claim 5, further comprising a processor and the buffer information passed to the "non-core function port" further comprises a time stamp, wherein, the processor time stamps frames upon receipt, and wherein, a time out value is calculated that ensures that the frame is discarded within R_-- A_-- TOV.

17. A method of switching data frames, each data frame having a frame beginning, in a network having a plurality of ports and a central memory including a plurality of memory modules, the method comprising:

receiving a data frame at a first port;

determining a destination port;

striping the data frame across the plurality of memory modules in the central memory;

generating a message indicating which memory module of the plurality of memory modules stores the beginning of the frame; and

sending the message to the destination port.

18. The method of claim 17 wherein the step of striping the data frame across the plurality of memory modules in the central memory includes writing the beginning of the data frame to a next available memory module.

19. The method of claim 17 further comprising the step of sending the bit-sliced data frame from the plurality of memory modules to the destination port.

20. A method of switching data frames, each data frame having a frame beginning, in a network having a plurality of ports and a central memory including a plurality of memory modules, the method comprising:

receiving a data frame at a first port;

determining a destination port;

bit-slicing the data frame across the plurality of memory modules in the central memory;

generating a buffer descriptor indicating which memory module of the plurality of memory modules stores the beginning of the bit-sliced data frame;

sending the buffer descriptor to the destination port; and

sending the bit-sliced data frame from the plurality of memory modules to the destination port.