Method and apparatus for controlling I/O channels responsive to an availability of a plurality of I/O devices to transfer data

• US 5,894,560 A
• Filed: 08/26/1996
• Issued: 04/13/1999
• Est. Priority Date: 03/17/1995
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Carmichael, Richard D., Winchell, Michael A., Ward, Joel M.
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US08/702,998
• Time in Patent Office: 960 Days
• Field of Search: 395/825, 395/826, 395/827, 395/840, 395/841, 395/844, 395/845, 395/800, 395/600
• US Class Current: 710/25
• CPC Class Codes: G06F 13/122 where hardware performs an I/O function other than control of data transfer
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

An apparatus and method for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to chain contiguous DMA scatter gather sub blocks of a PRD table for channel 0 with contiguous DMA scatter gather sub blocks of a PRD table for channel 1, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled based on the availability of data from the I/O device'"'"'s buffer memory, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.

Claims

1. A method for transferring blocks of data with a plurality of input/output (I/O) devices in a data processing system, comprising the step of:

interleaving DMA block transfers responsive to data transfer availability of at least two of the plurality of I/O devices.

2. The method of claim 1 wherein the interleaving DMA block transfers step uses a single data manager.

3. The method of claim 1 wherein the interleaving DMA block transfers step is based on actual data availability from the I/O devices during a read.

4. The method of claim 1 wherein the interleaving DMA block transfers step is based on buffer availability within the I/O devices during writes.

5. The method of claim 1 wherein the interleaving DMA block transfers step is used to interface two channels of a first bus with a channel of a second bus.

6. The method of claim 1 wherein slow I/O devices are controlled responsive to a large number of table entries, each table entry having a small block transfer size.

7. The method of claim 1 wherein faster I/O devices are controlled responsive to a small number of table entries, each table entry having a large block transfer size.