Variable timeout method for improving missing-interrupt-handler operations in an environment having I/O devices shared by one or more systems

• US 5,894,583 A
• Filed: 04/09/1996
• Issued: 04/13/1999
• Est. Priority Date: 04/09/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ripberger, Richard Anthony, Urbanejo, Luis Ricardo, Yudenfriend, Harry Morris, Johnson, Gavin Stuart
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US08/629,661
• Time in Patent Office: 1,099 Days
• Field of Search: 395/733-739, 395/868, 395/878, 395/185, 395/183, 395/200
• US Class Current: 710/48
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day

Abstract

Missing interrupt handler (MIH) software features for supporting a variable MIH timeout for I/O requests issued by an operating system (OS). The MIH timeout is varied to prevent a false indication of a failure in an I/O device operation, which is indicated if the MIH timeout occurs. By extending the MIH timeout, the I/O device is given more time to complete its operation, and the extension is provided when the device control unit (CU), or the OS, determines an I/O operation cannot complete before the shortest available MIH timeout. The length of a primary MIH timeout period is extended to a secondary MIH timeout period in response to the OS detecting that an I/O request has a long command that requires a long operating time in the I/O device, or a signal from the device'"'"'s CU indicating that the current operation in the I/O device is taking an excessive time without the device being in any error condition.

Claims

1. A method for use in a computer arrangement having a plurality of operating systems (OSs) in which each OS has a missing interrupt handler (MIH) process for detecting a failed input/output (I/O) device operation for an I/O request issued by the OS to an I/O subsystem, the OSs sharing at least one I/O controller connected to I/O devices, the MIH process comprising the steps of;

storing a plurality of MIH timeout extension values in the computer arrangement accessible to the MIH process including a primary timeout value and a secondary timeout value,

storing at least one CU threshold timeout value accessible to the CU,

sending an I/O request from the OS to the CU for an operation by an I/O device connected to the CU, and rejecting the I/O request by the CU if the I/O device is not then available for use by the I/O request,

starting a MIH timer process from a zero time value and using the primary timeout value as a current MIH timeout value for the I/O request when the I/O request is sent to the CU, and signalling an MIH timeout when and if the MIH timer process reaches a time equal to or greater than the current MIH timeout value,

contending by the I/O request with any other concurrent I/O requests in the CU for use of the I/O device,

initiating an CU threshold timer process from a zero time value to measure CU threshold elapsed time for the I/O request if the I/O request is rejected by the CU when the I/O device is busy,

indicating a CU threshold timeout if elapsed time measured by the CU threshold timer process is equal to or greater than the CU threshold timeout value,

CU signalling a long-busy interrupt to the OS when and if the CU threshold timer process indicates the CU threshold timeout,

replacing the current MIH timeout value with the MIH secondary timeout value for an OS timer process in response to the CU signalling of the long-busy interrupt, and

signalling the MIH timeout when and if the MIH timer process reaches an elapsed time equal to or greater than the MIH secondary timeout value to indicate the I/O device operation has failed.

2. A method of avoiding false detection of missing I/O interrupt signals by a operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices as defined in claim 1, further comprising the steps of:

storing at the I/O controller a subset of long command representations with associated timeout parameters,

comparing by the I/O controller a command code received with each command and codes stored with the long command representations in the stored subset,

accessing by the I/O controller a timeout parameter associated with any long command representation in the stored subset having a code equal to the command code received by the I/O controller for an I/O request of an OS, and

copying the timeout parameter into an OS storage, and communicating a concurrent interrupt signal from the I/O controller to the OS for the OS to use the timeout parameter to time when the I/O request is expected to be completed.

3. A MIH process as defined in claim 1, further comprising the steps of:

ending operation of the MIH timer process for the I/O request if and when the I/O device accepts the I/O request for an operation before occurrence of an MIH timeout.

4. A MIH process as defined in claim 1, further comprising the steps of:

ending operation of the CU threshold timer process for the I/O request if the I/O device accepts the I/O request for an operation before occurrence of the CU threshold timeout.

5. A MIH process as defined in claim 1, further comprising the steps of:

releasing CU resources used by the I/O request when the long-busy interrupt is signalled to the OS to enable the CU resources to be used by another I/O request, and

queuing the I/O request in an OS I/O queue while the I/O request is waiting for availability of the I/O device.

6. A MIH process as defined in claim 5, further comprising the steps of:

completion-signalling by the CU to the OS when the device becomes available for use by another I/O request, and

re-driving the I/O request by the OS in response to receiving the completion-signalling from the CU to re-issue the I/O request to the CU to enable the I/O request to again contend for use of the I/O device.

7. A MIH process as defined in claim 5, further comprising the steps of:

using one of a plurality of channel interface adapters in the CU as the CU resource used by the I/O request, and

releasing the channel interface adapter by the CU when and if the long-busy interrupt is sent to the OS by the CU.

8. A method for use in a computer arrangement having a plurality of operating systems (OSs) in which each OS has a missing interrupt handler (MIH) process for detecting a failed input/output (I/O) device operation for an I/O request issued by the OS to an I/O subsystem, the OSs sharing at least one I/O controller connected to I/O devices, the MIH process comprising the steps of:

storing a plurality of MIH timeout extension values in the computer arrangement accessible to the MIH process including a primary timeout value and a plurality of secondary timeout values,

storing a plurality of control unit (CU) threshold timeout values accessible to the CU including a first CU threshold timeout value and a plurality of secondary threshold timeout values,

sending an I/O request from the OS to the CU for an operation by an I/O device connected to the CU, and rejecting the I/O request by the CU if the I/O device is not then available for use by the I/O request,

starting an MIH timer process from a zero time value and initially using the primary timeout value as a current MIH timeout value for the I/O request when the I/O request is sent to the CU, and signalling an MIH timeout when and if the MIH timer process reaches a time equal to or greater than the current MIH timeout value,

contending by the I/O request with any other concurrent I/O requests in the CU for use of the I/O device,

initiating an CU threshold timer process to measure CU threshold elapsed time for the I/O request from a zero time value and initially using the primary threshold value as a current CU threshold value if the I/O request is rejected by the CU when the I/O device is busy,

indicating a CU threshold timeout if elapsed time measured by the CU threshold timer process is equal to or greater than the current CU threshold value,

CU signalling a long-busy interrupt to the OS when and if the CU threshold timer process indicates the CU threshold timeout,

replacing the current MIH timeout value with a next one of the plurality of MIH secondary timeout values for the OS timer process in response to the CU signalling of the long-busy interrupt, and replacing the current CU threshold value with a next one of the plurality of CU threshold values for the CU timer process in response to the CU signalling of the long-busy interrupt, and

signalling the MIH timeout when and if the MIH timer process reaches an elapsed time equal to or greater than the current MIH timeout value to indicate the I/O device operation has failed.

9. A MIH process as defined in claim 8, further comprising the steps of:

sizing each of the plurality of MIH secondary timeout extension values unequal to each other.

10. A MIH process as defined in claim 9, further comprising the steps of:

sizing each of the plurality of CU secondary threshold timeout values measure a shorter time period than a corresponding MIH secondary timeout extension value.

11. A method of avoiding false detection of missing I/O interrupt signals by an operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices, an I/O controller in the data processing system for receiving I/O requests issued by an OS for use of an I/O device connected to the I/O Controller, the method comprising the steps of:

delaying a received I/O request in the I/O Controller when an I/O device required by the I/O request is busy and non-available for use by the I/O request,

communicating a long-busy delay signal from the I/O Controller to the OS as an error interrupt with status information indicating the error interrupt to simulate a long-busy interrupt when the I/O Controller detects the delay has reached a predetermined threshold time from when the I/O request was received by the I/O Controller and the I/O Controller knows the I/O device is then operational and not available to the I/O request, and

extending a MIH (missing interrupt handler) primary timeout period by a predetermined time extension in response to the OS receiving the long-busy delay signal from the CU.

12. A data processing system executing a plurality of operating systems (OSs) having MIH handlers as defined in claim 11, further comprising the steps of:

simulating the long-busy delay signal from the CU to the OS by sending an error-indicating interrupt signal with status information indicating the error-indicating interrupt signal represents the long-busy interrupt signal.

13. A data processing system executing a plurality of operating systems (OSs) having MIH handlers as defined in claim 11, further comprising the steps of:

detecting by the OS a long-busy (LB) interrupt signal received in response to the redriving step as a rejection of the I/O request reissued by the OS for indicating a device needed is busy with another I/O request which contains a long command, and

further extending the MIH timeout interval for the OS when a long busy interrupt signal is received prior to the timeout occurring.

14. A method of avoiding false detection of missing I/O interrupt signals by a operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices as defined in claim 11, further comprising the steps of:

detecting a long command received by the CU by storing therein a set of parameters representing respective timeout values for various commands and the set of long commands possible and determining upon detection of a timeout whether or not any received command matches any parameter in the set.

15. A method of avoiding false detection of missing I/O interrupt signals by a operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices as defined in claim 11, further comprising the steps of:

starting a MIH timeout interval for a requester OS only when a request by the requestor OS is signalled as accepted by the CU for the I/O device.

16. A method of avoiding false detection of missing I/O interrupt signals by a operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices as defined in claim 11, further comprising the steps of:

storing for the I/O controller an identifier of each rejected OS for which a rejection was issued due to an existing long-busy indication, and

signalling a no-longer long-busy signal for each rejected OS indicated by the last storing step when execution completes for the command for which the existing long-busy indication was set.

17. A method of avoiding false detection of missing I/O interrupt signals by a operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices as defined in claim 11, further comprising the steps of:

storing for each OS a primary MIH timeout interval and a secondary MIH timeout interval,

accessing and using by an OS the primary MIH timeout interval to detect for missing interrupts when a short command is issued by the OS for an I/O device, and

accessing and using by an OS the secondary MIH timeout interval to detect for missing interrupts when a long command is issued by the OS for an I/O device.

18. A method of avoiding false detection of missing I/O interrupt signals by a operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices as defined in claim 17, further comprising the steps of:

scanning a channel program associated with an I/O request to be made by an OS for using an I/O device to determine the existence of long commands in the channel program,

indicating if the channel program contains or does not contain any long command,

assigning a primary MIH timeout interval for detecting any missing interrupt for the I/O request if the channel program does not contain any long command, and

assigning a secondary MIH timeout interval for detecting any missing interrupt for the I/O request if the channel program does contain any long command to enable a MIH detection process to have short timeouts for detecting missing interrupts for short commands.

19. A method of avoiding false detection of missing I/O interrupt signals by a operating system (OS) in a data processing system having one or more OSs capable of sharing I/O devices as defined in claim 18, further comprising the steps of:

storing in each I/O controller a primary MIH timeout interval and a secondary MIH timeout interval for use with commands directed to devices connected to the I/O controller, and

accessing the primary MIH timeout interval and the secondary MIH timeout interval from the I/O controller for storage accessibility by the OS prior to issuing any command for the I/O controller.