Method of making stepped edge structure of an EEPROM tunneling window

• US 5,895,240 A
• Filed: 06/30/1997
• Issued: 04/20/1999
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chung, Ming-Chih, Lin, Jyh-Feng, Chuang, Kuen-Joung
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/884,916
• Time in Patent Office: 659 Days
• Field of Search: 438/259, 438/260, 438/264, 438/589, 438/762, 438/763
• US Class Current: 438/260
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

Claims

1. A method of fabricating a tunnel oxide layer for a memory device comprising the steps of:

a) forming a first oxide layer over a surface of a semiconductor substrate;

said substrate having a channel region;

said substrate having a tunneling region surrounded by said channel region;

b) forming a first photoresist layer having a first photoresist opening over a portion of said channel region;

c) etching a first portion of said first oxide layer through said first photoresist opening at least over said tunneling region exposing said substrate forming a first tunneling opening;

d) forming a second oxide layer over said exposed substrate and said first oxide layer;

e) forming a second photoresist layer over said second oxide layer;

said second photoresist layer having a second photoresist opening;

said second photoresist opening is smaller than said first photoresist opening;

said second photoresist opening exposing said tunneling region;

f) etching said second oxide layer through said second opening exposing said substrate surface and forming a first step;

g) forming a third oxide layer over said exposed substrate, said first oxide layer and said second oxide layer;

thereby propagating said first step and whereby the oxide thinning edge effect is eliminated by said first step.

2. The method of claim 1 which further includes said first photoresist opening is defined by a first exposure through a first photolithography optical mask;

said second photoresist opening is defined by a second exposure through said first photolithography optical mask;

said second exposure is longer than said first exposure thereby said second photoresist opening is smaller than said first photoresist opening.

3. The method of claim 1 wherein said first oxide layer has thickness in a range of between about 25 and 150 Å

.

4. The method of claim 1 wherein said second oxide layer has a thickness in a range of between about 25 and 75 Å

.

5. The method of claim 1 wherein said second photoresist opening is smaller than said first photoresist opening by between about 0.02 and 0.07 μ

m.

6. The method of claim 1 wherein said third oxide layer has a thickness in a range of between about 40 and 125 Å

.

7. The method of claim 1 wherein said first step has a width in a range of between about 0.02 μ

m and 0.07 μ

m and a height between about 115 and 155 Å

.

13. The method of claim 1 wherein said first tunneling opening has an open dimension in a range of between about 0.3 and 1.0 μ

m .

14. The method of claim 1 wherein said first step has a width in a range of between about 100 Å

and 0.5 μ

m.

8. A method of fabricating a tunnel oxide layer for a memory device;

comprising the steps of;

a) forming a first oxide layer over a surface of a semiconductor substrate;

said substrate having a channel region;

said substrate having a tunneling region surrounded by said channel region;

b) forming a first photoresist layer having a first photoresist opening over a portion of said channel region;

said first photoresist opening defined by a first exposure through a first photolithography optical mask;

c) etching said first oxide layer through said first photoresist opening at least over said tunneling region exposing said substrate forming a first tunneling opening;

d) forming a second oxide layer over said exposed substrate and said first oxide layer;

e) forming a second photoresist layer over said second oxide layer;

said second photoresist layer having a second photoresist opening;

said second photoresist opening is smaller than said first photoresist opening;

said second photoresist opening exposing said tunneling region;

said second photoresist opening is smaller than said first photoresist opening by a distance of between about 0.02 and 0.07 μ

m;

said second photoresist opening is defined by a second exposure through said first photolithography optical mask;

said second exposure is longer than said first exposure thereby said second photoresist opening is smaller than said first photoresist opening;

f) etching said second oxide layer through said second opening exposing said substrate surface and forming a first step;

g) forming a third oxide layer over said exposed substrate, said first oxide layer and said second oxide layer;

thereby propagating said first step and whereby the oxide thinning edge effect is eliminated by said first step;

said first step has a width in a range of between about 0.02 μ

m and 0.07 μ

m and more preferably about 0.05 μ

m and a height between about 115 and 155 Å and

more preferably of about 125 Å

.

9. The method of claim 8 wherein said second oxide layer has a thickness in a range of between about 25 and 75 Å

.

10. The method of claim 8 wherein said first oxide layer has a thickness in a range of between about 25 and 150 Å

.

11. The method of claim 8 wherein said third oxide layer has a thickness in a range of between about 40 and 125 Å

.

12. A method of fabricating a tunnel oxide layer for a memory device;

comprising the steps of;

a) forming a first oxide layer over a surface of a semiconductor substrate;

said substrate having a channel region;

b) etching a portion of said first oxide layer forming a first tunneling opening and first step;

c) etching said first oxide layer forming a second tunneling opening exposing said channel region and forming a second step, said second tunneling opening having an open dimension larger than said first tunneling opening;

d) oxidizing said substrate forming a tunnel oxide layer over said channel region whereby the oxide thinning edge effect is eliminated by said step.

15. A method of fabricating a tunnel oxide layer for a memory device;

comprising the steps of;

a) forming a first oxide layer over a surface of a semiconductor substrate;

said substrate having a channel region;

b) forming a first photoresist layer having a first photoresist opening over a portion of said channel region;

c) etching a first portion of said first oxide layer said first photoresist opening forming a first tunneling opening;

d) forming a second photoresist layer having a second photoresist opening over a portion of said channel region;

said second photoresist opening having an open dimension larger than said first photoresist opening;

e) etching said first oxide layer through a portion of said second photoresist opening forming a second tunneling opening exposing said channel region and forming a second step, said second tunneling opening having an open dimension larger than said first tunneling opening;

f) oxidizing said substrate forming a tunnel oxide layer over said channel region whereby the oxide thinning edge effect is eliminated by said step.