Demand-based larx-reserve protocol for SMP system buses

• US 5,895,495 A
• Filed: 03/13/1997
• Issued: 04/20/1999
• Est. Priority Date: 03/13/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Williams, Derek Edward, Arimilli, Ravi Kumar, Lewis, Jerry Don, Dodson, John Steven
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Chow, Christopher S.
• Application Number:
  US08/815,647
• Time in Patent Office: 768 Days
• Field of Search: 711/141, 711/122, 711/119, 711/121, 711/156, 711/143, 711/145, 711/146
• US Class Current: 711/156
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies

Abstract

A method of handling load-and-reserve instructions in a multi-processor computer system wherein the processing units have multi-level caches. Symmetric multi-processor (SMP) computers use cache coherency to ensure the same values for a given memory address are provided to all processors in the system. Load-and-reserve instructions used, for example, in quick read-and-write operations, can become unnecessarily complicated. The present invention provides a method of accessing values in the computer'"'"'s memory by loading the value from the memory device into all of said caches, and sending a reserve bus operation from a higher-level cache to the next lower-level cache only when the value is to be cast out of the higher cache, and thereafter casting out the value from the higher cache after sending the reserve bus operation. This procedure is preferably used for all caches in a multi-level cache architecture, i.e., when the value is to be cast out of any given cache, a reserve bus operation is sent from the given cache to the next lower-level cache (i.e., the adjacent cache which lies closer to the bus), but the reserve bus operation is not sent to all lower caches. Any attempt by any other processing unit in the computer system to write to an address of the memory device which is associated with the value will then be forwarded to all higher-level caches. The marking of the block as reserved is removed in response to any such attempt to write to the address.

Claims

1. A method of accessing a value from a memory device for use in a processing unit of a multi-processor computer system, the processing unit having at least first and second caches wherein contents of the first cache are included in the second cache, comprising the steps of:

loading the value from the memory device into all of said caches;

marking the first cache which receives the value as reserved;

when the value is to be cast out of the first cache, sending a reserve bus operation from the first cache to the second cache; and

casting out the value from the first cache after said sending of the reserve bus operation to the second cache.

2. The method of claim 1 further comprising the step of the second cache forwarding, to the first cache, any attempt by any other processing unit in the computer system to write to an address of the memory device which is associated with the value.

3. The method of claim 1 wherein the processing unit has a third cache, and further comprising the steps of:

when the value is to be cast out of the second cache, sending a reserve bus operation from the second cache to the third cache; and

casting out the value from the second cache after said sending of the reserve bus operation to the third cache.

4. The method of claim 1 wherein the processing unit has a plurality of caches in addition to the first and second caches, all of the caches being serially connected between a processor of the processing unit and a bus of the computer system, and further comprising the steps of:

when the value is to be cast out of any given cache, sending a reserve bus operation from the given cache to the adjacent cache which is closer to the bus; and

casting out the value from the given cache after said sending of the reserve bus operation to the adjacent cache.

5. The method of claim 1 wherein the first cache is connected to a processor of the processing unit and to the second cache, and the second cache is further connected to a bus of the computer system.

6. The method of claim 1 comprising the further step of the processing unit storing a new value in the memory device conditioned upon the first cache still being marked as reserved.

7. The method of claim 2 wherein any attempt to write to the address of the memory device is detected using a cache-coherency protocol.

8. The method of claim 2 comprising the further step of removing the marking of the cache as reserved, in response to any attempt to write to the address.

9. The method of claim 3 further comprising the step of the third cache forwarding, to the second cache, any attempts by any other processing unit in the computer system to write to an address of the memory device which is associated with the value.

10. The method of claim 9 further comprising the step of the second cache forwarding, to the first cache, the attempts by any other processing unit to write to the address.

11. A processing unit for a computer system, comprising:

a processor; and

a plurality of caches for providing values to said processor, said caches being arranged in levels and adapted to send a reserve bus operation from a higher-level cache to a next lower-level cache which contains the contents of the higher-level cache, prior to casting out a reserved block from said higher-level cache.

12. The processing unit of claim 11 wherein said caches include one or more on-board caches integrally packaged with said processor.

13. The processing unit of claim 11 wherein each said cache forwards, to all higher-level caches, any attempt by another processing unit to write to an address of a memory device which is associated with said block.

14. The processing unit of claim 13 wherein each said cache changes said reserved block to a not-reserved state in response to any attempt to write to said address.

15. The processing unit of claim 14 wherein any attempt to write to said address is detected using a cache-coherency protocol.

16. A multi-processor computer system comprising:

a memory device;

a bus connected to said memory device; and

a plurality of processing units each connected to said bus, at least one of said processing units having a plurality of caches arranged in levels, said caches adapted to send a reserve bus operation from a higher-level cache to a next lower-level cache which contains the contents of the higher-level cache, prior to casting out a reserved block from said higher-level cache.

17. The computer system of claim 16 wherein each said processing unit has a plurality of caches arranged in levels, all of said caches adapted to send a reserve bus operation from a higher-level cache to a next lower-level cache prior to casting out a reserved block from said higher-level cache.

18. The computer system of claim 16 wherein each said cache forwards, to all higher-level caches, any attempt by another processing unit to write to an address of a memory device which is associated with said block.

19. The computer system of claim 18 wherein each said cache changes said reserved block to a not-reserved state in response to any attempt to write to said address.

20. The computer system of claim 19 wherein any attempt to write to said address is detected using a cache-coherency protocol.