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MOS random access memory having array of trench type one-capacitor/one-transistor memory cells

  • US 5,895,946 A
  • Filed: 01/14/1998
  • Issued: 04/20/1999
  • Est. Priority Date: 03/19/1992
  • Status: Expired due to Fees
First Claim
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1. A random access memory device comprising:

  • a semiconductor substrate including an overlying first and an underlying second semiconductive layer of a first conductivity type with a third semiconductor layer of a second conductivity type sandwiched therebetween in a stacked manner, said substrate including an array of rows and columns of trenches formed to vertically extend through the overlying first semiconductive layer to terminate in the third semiconductive layer;

    a plurality of capacitors formed in lower portions of said trenches, respectively, each of said capacitors including a plate electrode formed on a side surface of each of said lower portions of said trenches and on a bottom surface of each of said trenches consisting of said third semiconductive layer, a capacitor insulation film formed to cover said plate electrode and a storage electrode formed on said capacitor insulation film and buried in each of said lower portions of said trenches;

    a plurality of MOS transistors formed in upper portions of said trenches, respectively, each of said transistors includinga channel formation region composed of a semiconductor film formed above a side surface of each of said upper portions of said trenches with a second insulating film interposed therebetween, said second insulating film being formed continuously with said capacitor insulating film;

    a gate electrode formed above said channel formation region with a gate insulation film interposed therebetween and insulatively buried in each of said upper portions of said trenches, said gate electrode being formed so as to continuously extend on a surface of said substrate in a direction of said rows to serve as a word line;

    a first impurity-doped region formed on said storage electrode and connected to a lower end of said channel formation region;

    a second impurity-doped region formed, above said surface of said substrate, beside said gate electrode and along one side of said word line; and

    a plurality of bit lines each connected to said second impurity-doped region and formed continuously in a direction of said columns above said surface of said substrate,wherein said second impurity-doped region is shared by an adjacent one of said transistors arranged in the direction of said columns and is connected, only when said gate electrode is supplied with an activation signal to make said channel formation region conductive, to an adjacent one of said second impurity-doped region through an upper end of said channel formation region interposed therebetween on said surface of said substrate, thereby being continuously linked in the direction of said columns to be served as another bit line.

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