MOS random access memory having array of trench type one-capacitor/one-transistor memory cells

• US 5,895,946 A
• Filed: 01/14/1998
• Issued: 04/20/1999
• Est. Priority Date: 03/19/1992
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hamamoto, Takeshi, Horiguchi, Fumio
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US09/006,898
• Time in Patent Office: 461 Days
• Field of Search: 257/301, 257/302, 257/305
• US Class Current: 257/302
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.

Claims

1. A random access memory device comprising:

a semiconductor substrate including an overlying first and an underlying second semiconductive layer of a first conductivity type with a third semiconductor layer of a second conductivity type sandwiched therebetween in a stacked manner, said substrate including an array of rows and columns of trenches formed to vertically extend through the overlying first semiconductive layer to terminate in the third semiconductive layer;

a plurality of capacitors formed in lower portions of said trenches, respectively, each of said capacitors including a plate electrode formed on a side surface of each of said lower portions of said trenches and on a bottom surface of each of said trenches consisting of said third semiconductive layer, a capacitor insulation film formed to cover said plate electrode and a storage electrode formed on said capacitor insulation film and buried in each of said lower portions of said trenches;

a plurality of MOS transistors formed in upper portions of said trenches, respectively, each of said transistors including

a channel formation region composed of a semiconductor film formed above a side surface of each of said upper portions of said trenches with a second insulating film interposed therebetween, said second insulating film being formed continuously with said capacitor insulating film;

a gate electrode formed above said channel formation region with a gate insulation film interposed therebetween and insulatively buried in each of said upper portions of said trenches, said gate electrode being formed so as to continuously extend on a surface of said substrate in a direction of said rows to serve as a word line;

a first impurity-doped region formed on said storage electrode and connected to a lower end of said channel formation region;

a second impurity-doped region formed, above said surface of said substrate, beside said gate electrode and along one side of said word line; and

a plurality of bit lines each connected to said second impurity-doped region and formed continuously in a direction of said columns above said surface of said substrate,

wherein said second impurity-doped region is shared by an adjacent one of said transistors arranged in the direction of said columns and is connected, only when said gate electrode is supplied with an activation signal to make said channel formation region conductive, to an adjacent one of said second impurity-doped region through an upper end of said channel formation region interposed therebetween on said surface of said substrate, thereby being continuously linked in the direction of said columns to be served as another bit line.

2. A random access memory comprising:

a semiconductor substrate having a surface in which a plurality of trenches are formed;

a plurality of parallel data transfer lines on said substrate; and

an array of memory cells on said substrate, said memory cells being divided into a plurality of cell units which are coupled at nodes to said data transfer lines, respectively, and each of said cell units including a preselected number of memory cells each having a capacitor and a first and a second transistor,

wherein said capacitor and said first and said second transistor of each of said memory cells are stacked in a corresponding one of said trenches in such a manner that said first transistor and said second transistor overlie said capacitor in said corresponding one of said trenches,

said capacitor formed in each of lower portions of said trenches has an insulative storage electrode buried in each of said lower portions of said trenches,

said first transistor and said second transistor formed in each of upper portions of said trenches comprise;

a channel formation region composed of a semiconductor film formed above and around a side wall of each of said upper portions of said trenches with a second insulating film interposed therebetween, said channel formation region being shared by said first transistor and said second transistor;

a gate electrode formed above said channel formation region with a gate insulating film interposed therebetween and insulatively buried in each of said upper portions of said trenches, said gate electrode being shared by said first transistor and second transistor and being formed so as to extend on said surface of said substrate in a direction substantially perpendicular to said parallel data transfer lines to serve as a word line;

a first impurity-doped region formed on said storage electrode and connected to a lower end of said channel formation region;

a second impurity-doped region insulatively formed on said surface of said substrate, beside said gate electrode and along one side of said word line, and connected to an upper end of said channel formation region, said first and said second impurity-doped region constituting said first transistor with said gate electrode; and

a third impurity-doped region insulatively formed on said surface of said substrate at an opposite side of said second impurity-doped region with said gate electrode interposed therebetween, beside said gate electrode and along another side of said word line, and formed to be separated from said second impurity-doped region, said second and said third impurity-doped region and said channel formation region constituting said second transistor with said gate electrode,

each of said memory cells comprises said first transistor and said second transistor, thereby to form a preselected number of first transistors and second transistors, which include the preselected number of said third impurity-doped regions corresponding to the preselected number of said memory cells, and

the preselected number of said memory cells are series connected in such a manner that said third impurity-doped region of one of said second transistors is connected to said second region of another of said second transistors adjacent to said one of said second transistors and that a thermal one of said third regions forms one of said nodes at which each of said cell units is coupled to a corresponding one of said data transfer lines.

3. The random access memory according to claim 2, wherein each of said memory cells includes a third transistor comprised of said first impurity-doped region, said channel formation region, said third impurity-doped region and said gate electrode formed above said channel formation region with the gate insulating film interposed therebetween.