MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches

• US 5,895,951 A
• Filed: 04/05/1996
• Issued: 04/20/1999
• Est. Priority Date: 04/05/1996
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Megamos Corporation
• Inventors: So, Koon Chong, Hshieh, Fwu-Iuan, Tsui, Yan Man, Lin, True-Lon, Nim, Danny Chi
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/628,493
• Time in Patent Office: 1,110 Days
• Field of Search: 257/329, 257/330, 257/331, 257/339, 257/341, 257/342
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a MOSFET device which includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough. Each of the vertical cells is surrounded by a polysilicon layer acting as a gate for controlling the source-to-drain current through the channel. The MOSFET device further include a plurality of doping trenches filled with trench-filling materials, The MOSFET device further includes a plurality of deep-doped regions disposed underneath the doping trenches wherein the deep-doped region extends downwardly to a depth which is substantially a sum of an implant depth of the deep-doped region and a vertical diffusion depth below a bottom of the doping trenches.

Claims

1. A MOSFET vertical cell formed in a substrate includes a source, a drain, and a channel for conducting source-to-drain current therethrough across a body region wherein said vertical cell being surrounded by a polysilicon layer acting as a gate for controlling said source-to-drain current through said channel, said MOSFET cell further comprising:

a doping trench filled with a trench-filling material;

a deep-doped region disposed underneath said doping trench wherein said deep-doped region extends downwardly to substantially a total depth of an implant depth of said deep-doped region and a vertical diffusion depth below a bottom of said doping trench whereby said deep-doped region defining a buried region disposed below said body region; and

said doping trench includes an insulation layer insulating said trench filling material from said substrate and said gate, and said doping trench is employed only for implanting dopant ions therethrough and serving no active electrical functions.

2. The MOSFET vertical cell as recited in claim 1 wherein:

said doping trench disposed substantially at the center of said vertical cell with said deep-doped region disposed thereunder near a center portion of said vertical cell.

3. The MOSFET vertical cell as recited in claim 1 wherein:

said doping trench being filled with a trench filling material of polysilicon with said deep-doped region disposed thereunder.

4. The MOSFET vertical cell as recited in claim 1 wherein:

said doping trench filled with said trench filling material with said deep-doped region disposed thereunder is electrically connected to said source.

5. The MOSFET vertical cell as recited in claim 1 wherein:

said doping trench filled with said trench filling material with said deep-doped region disposed thereunder is electrically insulated from said source.

6. The MOSFET vertical cell as recited in claim 1 further comprising:

a lower deep-doped region disposed lower than said deep-doped region wherein said lower deep doped region is doped with impurities of a different conductivity type than a conductivity type of said deep-doped region.

7. A MOSFET device formed in a substrate includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough across a body region wherein each of said vertical cells being surrounded by a polysilicon layer acting as a gate for controlling said source-to-drain current through said channel, said MOSFET device further comprising:

a plurality of doping trenches filled with a trench-filling material;

a plurality of deep-doped regions disposed underneath said doping trenches wherein each of said deep-doped regions extends downwardly to substantially a total depth of an implant depth of said deep-doped region and a vertical diffusion depth below a bottom of a corresponding doping trench whereby each of said deep-doped regions defining a buried region disposed below said body region; and

each of said doping trenches included an insulation layer insulating said trench filling material from said substrate and said doping trench is employed only for implanting dopant ions there through and serving no active electrical function.

8. The MOSFET device as recited in claim 7 wherein:

each of said doping trenches disposed substantially at the center of one of said vertical cells with said deep-doped region disposed thereunder near a center portion of said vertical cell.

9. The MOSFET device as recited in claim 7 wherein:

each of said doping trenches being filled with a trench filling material of polysilicon with one of said deep-doped regions disposed thereunder.

10. The MOSFET device as recited in claim 9 wherein:

each of said doping trenches disposed substantially at the center of one of said vertical transistor cells.

11. A vertical power transistor cell formed in a substrate includes a source, a drain, and a channel for conducting source-to-drain current therethrough across a body region wherein said vertical cell being surrounded by a polysilicon layer acting as a gate for controlling said source-to-drain current through said channel, said power transistor cell further comprising:

a doping trench filled with a trench-filling material wherein said doping trench includes an insulation layer insulating said trench filling material from said substrate and said gate, and said doping trench is employed only for implanting dopant ions therethrough and serving no active electrical functions;

a deep-doped region disposed underneath said doping trench wherein said deep-doped region extends downwardly to substantially a total depth of an implant depth of said deep-doped region and a vertical diffusion depth below a bottom of said doping trench whereby said deep-doped region defining a buried region disposed below said body region; and

a lower deep-doped region disposed lower than said deep-doped region wherein said lower deep doped region is doped with impurities of a different conductivity type than a conductivity type of said deep-doped region.