Trench MOSFET with multi-resistivity drain to provide low on-resistance

• US 5,895,952 A
• Filed: 08/21/1996
• Issued: 04/20/1999
• Est. Priority Date: 12/30/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K., Darwish, Mohamed N.
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/701,035
• Time in Patent Office: 972 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/341, 257/408
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOSFET switch with a gate formed in a trench has a drain which includes a region of relatively high resistivity adjacent the trench and a region of relatively low resistivity further away from the trench. The drain may also include a "delta" layer having even lower resistivity in a central region of the MOSFET cell. The high resistivity region limits the strength of the electric field at the edge of the trench (particularly where there are any sharp corners) and thereby avoids damage to the gate oxide layer. The central "delta" layer helps to insure that any breakdown will occur near the center of the MOSFET cell, away from the gate oxide, and to lower the resistance of the MOSFET when it is in an on condition.

Claims

1. A MOSFET comprising:

a semiconductor member having a trench formed therein and a gate positioned in said trench;

a source region of a first conductivity type located in said semiconductor member adjacent said trench;

a body region of a second conductivity type located in said semiconductor member adjacent said source region;

a drain region of said first conductivity type located in said semiconductor member adjacent said body region, said drain region comprising;

a heavily doped region;

a drift region overlying and adjoining said heavily-doped region and having a concentration of dopant of said first conductivity type lower than a concentration of dopant of said first conductivity type in said heavily-doped region; and

a region of high resistivity adjacent a bottom of said trench, said region of high resistivity having a concentration of dopant of said first conductivity type lower than a concentration of dopant of said first conductivity type in said drift region; and

wherein said MOSFET includes a cell bounded on at least two sides by said gate, said MOSFET further comprising a delta doped layer separated laterally from said trench and located below said body region in a central region of said cell, said delta doped layer having a concentration of dopant of said first conductivity type greater than said concentration of dopant of said first conductivity type in said region of high resistivity.

2. The MOSFET of claim 1 wherein said region of high resistivity forms a PN junction with said body region.

3. The MOSFET of claim 1 wherein said delta doped layer is bordered by said drift region, said body region and said region of high resistivity.

4. The MOSFET of claim 1 wherein said delta doped layer is bordered by said body region and said region of high resistivity.

5. The MOSFET of claim 1 wherein said region of high resistivity and said drift region are formed in an epitaxial layer.

6. The MOSFET of claim 5 wherein said epitaxial layer is formed on a surface of a substrate.

7. The MOSFET of claim 1 wherein said region of high resistivity abuts a corner of said trench.

8. The MOSFET of claim 1 wherein said delta doped layer extends to a level below a bottom of said trench.

9. The MOSFET of claim 1 wherein said body region includes a deep central heavily-doped region which abuts a top boundary of said delta doped layer.

10. The MOSFET of claim 1 wherein said body region includes a deep central heavily-doped region.

11. The MOSFET of claim 10 wherein said deep central heavily-doped region abuts a top boundary of said delta doped layer.

12. The MOSFET of claim 10 wherein said deep heavily-doped central region is separated from said delta doped layer.

13. The MOSFET of claim 1 wherein said cell is surrounded by a gate comprising a grid of polygonal shapes.

14. The MOSFET of claim 1 wherein said cell is formed between a gate comprising parallel stripes.

15. The MOSFET of claim 1 wherein said heavily-doped region overlies a lower region of said second conductivity type.

16. The MOSFET of claim 15 further comprising a sinker region of said first conductivity type, said sinker region extending between said heavily-doped region and a surface of said semiconductor member.

17. The MOSFET of claim 2 wherein at least a portion of said PN junction is oriented parallel to a top surface of said semiconductor member.

18. A MOSFET comprising:

a semiconductor member having a trench formed therein and a gate positioned in said trench, said gate defining a MOSFET cell which is bounded on at least two sides by said gate;

a source region of a first conductivity type located in said semiconductor member adjacent said trench;

a body region of a second conductivity type located in said semiconductor member adjacent said source region; and

a drain region of said first conductivity type located in said semiconductor member adjacent said body region, said drain region comprising;

a heavily doped region;

a drift region overlying and adjoining said heavily-doped region and having a concentration of dopant of said first conductivity type lower than a concentration of dopant of said first conductivity type in said heavily-doped region; and

a region of high resistivity adjacent a bottom of said trench, said region of high resistivity having a concentration of dopant of said first conductivity type lower than a concentration of dopant of said first conductivity type in said drift region, said MOSFET further comprising;

a delta doped layer separated laterally from said trench and located below said body region in a central region of said cell, said delta doped layer having a resistivity lower than a resistivity in said region of high resistivity.

19. A trench MOSFET having a multi-resistivity drain, said MOSFET comprising:

a substrate;

a trench formed in said substrate, a gate insulated from said substrate being positioned in said trench;

a source region of a first conductivity type located adjacent a top surface of said substrate and a side wall of said trench;

a body region of a second conductivity type located adjacent said source region and said side wall; and

a multi-resistivity drain region of said first conductivity type located adjacent a bottom of said trench and below said body region, said multi-resistivity drain region comprising;

a first region of a relatively low resistivity;

a second region having a resistivity greater than the resistivity of said first region, said second region being located adjacent to and generally above said first region; and

a third region having a resistivity greater than the resistivity of said second region, said third region being located generally above said second region and abutting a bottom of said trench, and

a fourth region having a resistivity less than the resistivity of the second region;

wherein said MOSFET includes a cell bounded on at least two sides by said gate, said fourth region being located generally at a central region of said cell and being laterally spaced apart from said trench.

20. The MOSFET of claim 19 wherein said first region has a resistivity of about 3.0 mΩ

-cm.

21. The MOSFET of claim 19 wherein said second region has a dopant concentration of 5×

10¹⁴ to 5×

10¹⁶ cm^-3.

22. The MOSFET of claim 21 wherein said second region has a dopant concentration of about 6×

10¹⁵ cm^-3.

23. The MOSFET of claim 21 wherein said second region has a resistivity of about 0.8 Ω

-cm.

24. The MOSFET of claim 19 wherein said third region has a dopant concentration of 3×

10¹⁴ to 3×

10¹⁵ cm^-3.

25. The MOSFET of claim 24 wherein said third region has a dopant concentration of about 3×

10¹⁵ cm^-3.

26. The MOSFET of claim 24 wherein said third region has a resistivity of about 1.5 Ω

-cm.

27. The MOSFET of claim 19 wherein said third region abuts a point on a boundary of said trench where an electric field reaches a maximum when said MOSFET is turned off in the presence of a voltage difference between said source and drain regions.

28. A trench MOSFET having a multi-resistivity drain, said MOSFET comprising:

a substrate;

a trench formed in said substrate, a gate insulated from said substrate being positioned in said trench;

a source region of a first conductivity type located adjacent a top surface of said substrate and a side wall of said trench;

a body region of a second conductivity type located adjacent said source region and said side wall; and

a multi-resistivity drain region of said first conductivity type located adjacent a bottom of said trench and below said body region, said multi-resistivity drain region comprising;

a first region of a relatively low resistivity;

a second region having a resistivity greater than the resistivity of said first region, said second region being located adjacent to and generally above said first region; and

a third region having a resistivity greater than the resistivity of said second region, said third region being located generally above said second region and abutting a bottom of said trench and said body region, said MOSFET comprising a cell bounded on at least two sides by said trench, said drain region further comprising a fourth region which intersects a midpoint of said cell and which is at least partially bounded by said third region, said fourth region having a resistivity less than the resistivity of one of said second and third regions, a lower boundary of said fourth region abutting an upper boundary of said second region.

29. The MOSFET of claim 28 wherein said fourth region has a dopant concentration of about 3×

10¹⁶ cm^-3.

30. The MOSFET of claim 28 wherein a lateral boundary of said fourth region is separated from a side wall of said trench.

31. The MOSFET of claim 28 wherein said fourth region extends laterally to a side wall of said trench.

32. The MOSFET of claim 28 wherein an upper boundary of said fourth region abuts a lower boundary of said body region.

33. The MOSFET of claim 28 wherein a lower boundary of said fourth region is separated from an upper boundary of said second region.

34. The MOSFET of claim 28 wherein said body region includes a second heavily-doped region.

35. The MOSFET of claim 34 wherein said second heavily-doped region abuts an upper boundary of said fourth region.

36. The MOSFET of claim 34 wherein said second heavily-doped region is separated from an upper boundary of said fourth region.