MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch
First Claim
1. A method for forming a transistor, comprising:
- providing a gate dielectric layer interposed between a semiconductor substrate and a layer of polysilicon;
removing select regions of said layer of polysilicon and said gate dielectric to create a gate conductor dielectrically spaced upon said semiconductor substrate between openings to said semiconductor substrate;
forming a dual layer etch stop upon the gate conductor and the semiconductor substrate within said openings;
depositing a layer of spacer material across the entire said etch stop; and
while retaining said dual layer etch stop, removing the layer of spacer material along substantially horizontal surfaces faster than substantially vertical surfaces to create a spacer which abuts with a region of said etch stop proximate to a pair of opposed sidewall surfaces of said gate conductor.
3 Assignments
0 Petitions
Accused Products
Abstract
A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a series of laterally spaced surfaces to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. The multilayer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The polysilicon spacer is formed by an anisotropic etch, and the pre-existing etch stop prevents the anisotropic etch from damaging the source/drain and gate conductor regions beneath the etch stop. Further, the etch stop allows removal of the overlying oxide as well as the entire polysilicon during times when the multi-layer spacer is entirely removed. Removal of the various layers does not damage the underlying substrate due to the presence of the etch stop. The etch stop preferably comprises a nitride layer overlying an oxide layer, wherein the oxide layer can either be deposited or grown.
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Citations
24 Claims
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1. A method for forming a transistor, comprising:
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providing a gate dielectric layer interposed between a semiconductor substrate and a layer of polysilicon; removing select regions of said layer of polysilicon and said gate dielectric to create a gate conductor dielectrically spaced upon said semiconductor substrate between openings to said semiconductor substrate; forming a dual layer etch stop upon the gate conductor and the semiconductor substrate within said openings; depositing a layer of spacer material across the entire said etch stop; and while retaining said dual layer etch stop, removing the layer of spacer material along substantially horizontal surfaces faster than substantially vertical surfaces to create a spacer which abuts with a region of said etch stop proximate to a pair of opposed sidewall surfaces of said gate conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An integrated circuit, comprising:
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a transistor gate conductor dielectrically spaced above a semiconductor substrate; a dielectric etch stop structure comprising a substantially vertical portion and a substantially horizontal portion, wherein said substantially vertical portion extends along a sidewall surface of said gate conductor and said substantially horizontal portion extends along an upper surface of said semiconductor substrate outward from said sidewall surface; and a pair of spacer structures, each arranged adjacent an exposed vertical sidewall of said vertical portion and upon an exposed upper surface of said horizontal portion, wherein each spacer structure comprises a polysilicon portion and an oxide portion, and wherein an upper surface of said spacer structure is at a higher elevation level than an upper surface of said gate conductor. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification