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MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch

  • US 5,895,955 A
  • Filed: 01/10/1997
  • Issued: 04/20/1999
  • Est. Priority Date: 01/10/1997
  • Status: Expired due to Term
First Claim
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1. A method for forming a transistor, comprising:

  • providing a gate dielectric layer interposed between a semiconductor substrate and a layer of polysilicon;

    removing select regions of said layer of polysilicon and said gate dielectric to create a gate conductor dielectrically spaced upon said semiconductor substrate between openings to said semiconductor substrate;

    forming a dual layer etch stop upon the gate conductor and the semiconductor substrate within said openings;

    depositing a layer of spacer material across the entire said etch stop; and

    while retaining said dual layer etch stop, removing the layer of spacer material along substantially horizontal surfaces faster than substantially vertical surfaces to create a spacer which abuts with a region of said etch stop proximate to a pair of opposed sidewall surfaces of said gate conductor.

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