Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer
First Claim
1. A transistor formed in an intrinsic silicon layer on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×
- 1011 cm-2, said transistor made by the process comprising the steps of;
epitaxially depositing a layer of silicon on a surface of a sapphire substrate;
implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;
selecting an areal portion of said silicon on sapphire and maintaining said areal portion at or below a temperature of approximately zero degrees centigrade (0°
C.) such that the temperature throughout said areal portion is substantially uniform during said ion implanting step;
annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and
controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°
C. during any annealing and/or processing procedures performed subsequent to said ion implanting step which expose said layer of silicon to a non-oxidizing ambient environment, thereby maintaining an areal density of electrically active states in regions of said silicon layer not intentionally doped which is less than approximately 5×
1011 cm-2.
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Abstract
A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.
Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.
Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. |Vtn |=|Vtp |).
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Citations
3 Claims
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1. A transistor formed in an intrinsic silicon layer on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×
- 1011 cm-2, said transistor made by the process comprising the steps of;
epitaxially depositing a layer of silicon on a surface of a sapphire substrate; implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region; selecting an areal portion of said silicon on sapphire and maintaining said areal portion at or below a temperature of approximately zero degrees centigrade (0°
C.) such that the temperature throughout said areal portion is substantially uniform during said ion implanting step;annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°
C. during any annealing and/or processing procedures performed subsequent to said ion implanting step which expose said layer of silicon to a non-oxidizing ambient environment, thereby maintaining an areal density of electrically active states in regions of said silicon layer not intentionally doped which is less than approximately 5×
1011 cm-2. - View Dependent Claims (2, 3)
- 1011 cm-2, said transistor made by the process comprising the steps of;
Specification