Static pulsed cross-coupled level shifter and method therefor

• US 5,896,045 A
• Filed: 05/05/1997
• Issued: 04/20/1999
• Est. Priority Date: 05/05/1997
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Siegel, Joshua, Sanchez, Hector, Chao, Chai-Chin
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Duong, Qui Van
• Application Number:
  US08/851,261
• Time in Patent Office: 715 Days
• Field of Search: 326/83, 326/86, 326/68, 326/80, 326/81, 326/9, 326/121
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

Level shifting circuit (36) utilizes self-timed pulse generators (40, 46) to provide a series of pulses in response to an input signal. The pulses are used to create a pulse of specified duration at a predetermined voltage level at first and second nodes (44, 45). In response to the predetermined pulses, shifted inverters (50, 52) provide a voltage output of either V_DDH or V_DDL, one of two different voltages which exist in a system utilizing the level shifter (36). In one form, level shifting circuit (36) may be used in an output buffer (60) to interface an integrated circuit designed to operate at a low supply voltage with additional integrated circuits operating at a higher supply voltage which could damage the gate oxide of the transistors in the low supply voltage integrated circuit.

Claims

1. A static cross-coupled level shifter circuit that receives an input signal at a first voltage or a second voltage and outputs an output signal at either the second voltage or a third voltage, comprising:

a first pulse generation circuit for generating a first pulse signal of a first duration;

a second pulse generation circuit for generating a second pulse signal of a second duration; and

a pair of cross-coupled inverters, wherein each inverter of the pair of cross-coupled inverters has an output that switches between the second and third voltages, in response to the first and second pulse signals;

the third voltage having a magnitude greater than a magnitude of the second voltage, the magnitude of the third voltage being large enough to destroy a gate oxide of any of a plurality of transistors used to implement the first and second pulse generation circuits and the pair of cross-coupled inverters and therefore never permitted to exist across a gate oxide of any of the plurality of transistors used to implement the first and second pulse generation circuits and the pair of cross-coupled inverters.

2. The circuit of claim 1, wherein a voltage level of the first pulse signal is a lower potential than the second voltage such that the inverter switches to the third voltage.

3. The circuit of claim 1, further comprising a dielectric protection circuit connected between each of the pulse generation circuits and the pair of cross-coupled inverters.

4. The circuit of claim 1, further comprising an output stage to form an output buffer, wherein one of the outputs of the pair of cross-coupled inverters is coupled to an input of the output stage of the output buffer.

5. The circuit of claim 4, further comprising one or more series-connected inverters receiving at least one output of the pair of cross-coupled inverters, wherein an output of the one or more series connected inverters is an input to the output stage of the output buffer.

6. The circuit of claim 4, further comprising an output signal voltage pull-up stage for selectively pulling up the output signal voltage substantially to the second voltage, thereby assisting the output stage to transition the output signal voltage from the first voltage to the third voltage.

7. The circuit of claim 1, wherein a dielectric breakdown voltage for at least one transistor of the static cross-coupled level shifter circuit is less than a difference between the first and third voltages and is greater than the difference between the second and third voltages.

8. A static cross-coupled level shifter circuit that receives an input signal having a first voltage or a second voltage, and provides an output signal having the second voltage or a third voltage, comprising:

a first plurality of delay elements connected in series that receives the input signal;

a first logic gate receiving an output of the first plurality of delay elements and the input signal;

first dielectric protection circuitry coupled to the output of the first logic gate;

a second plurality of delay elements connected in series that receives a logical inverse of the input signal;

a second logic gate receiving an output of the second plurality of delay elements and the logical inverse of the input signal;

second dielectric protection circuitry coupled to the output of the second logic gate;

a first pair of series-connected transistors having an input and an output, wherein the input of the first pair of series-connected transistors is connected to the first dielectric protection circuitry; and

a second pair of series-connected transistors having an input and an output, wherein the input of the second pair of series-connected transistors is connected to the second dielectric protection circuitry;

wherein the output of the first pair of series-connected transistors is connected to the input of the second pair of series-connected transistors, and the output of the second pair of series-connected transistors is connected to the input of the first pair of series-connected transistors.

9. The circuit of claim 8, wherein a dielectric breakdown voltage for at least one transistor of the static cross-coupled level shifter circuit is less than a difference between the first and third voltages and is greater than the difference between the second and third voltages.

10. The circuit of claim 8 wherein the circuit is comprised of complementary MOS transistors.

11. The circuit of claim 8, wherein the first pair of series-connected transistors includes a first transistor having a first terminal connected to the third voltage, and a second transistor having a first terminal connected to the second terminal of the first transistor and a second terminal connected to the second voltage, and wherein the second pair of series-connected transistors includes a first transistor having a first terminal connected to the third voltage, and a second transistor having a first terminal connected to a second terminal of the first transistor and having a second terminal connected to the second voltage, the first and second transistors of the first pair each having a control terminal connected together and to the second terminal of the first transistor of the second pair of series-connected transistors, the first and second transistors of the second pair each having a control terminal connected together and to the second terminal of the first terminal of the first pair of series-connected transistors.

12. A method for generating a voltage level shifted output in a level shifting circuit, the method comprising the steps of:

receiving an input signal having a first voltage or a second voltage;

voltage level shifting the input signal with circuitry having transistors with control electrodes of a first oxide thickness to an output signal varying between the second voltage and a third voltage, a differential between the first voltage and third voltage being large enough to damage or destroy the control electrodes of the first oxide thickness;

wherein there are no current conduction paths in the level shifting circuit that would permit current conduction between any of the first, second and third voltages during circuit operation when no logic state transitions are occurring.

13. The method according to claim 12, wherein the step of voltage level shifting further comprises the steps of:

generating pulses of an intermediate voltage between the first and second voltages, in response to a change in the input signal;

applying the pulses of the intermediate voltage to an input and output of a pair of cross-coupled shifted inverters; and

selectively driving the cross-coupled shifted inverters with the pulses, wherein the cross-coupled shifted inverters generate a level shifted output signal varying between the second voltage and the third voltage.

14. The method according to claim 12 further comprising the steps of:

performing a second voltage level shifting of the output signal with additional circuitry having transistors with control electrodes of the first oxide thickness, the second voltage level shifting providing a buffered output signal which varies between the first voltage and the third voltage.