Voltage controlled oscillator (VCO) frequency gain compensation circuit

• US 5,896,068 A
• Filed: 03/30/1998
• Issued: 04/20/1999
• Est. Priority Date: 12/12/1996
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moyal, Nathan Y.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/050,521
• Time in Patent Office: 386 Days
• Field of Search: 331/34, 331/57, 331/177 R, 331/177 V
• US Class Current: 331/34
• CPC Class Codes: H03B 2201/02 Varying the frequency of the oscillations by electronic means
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03L 2207/05 Compensating for non-linear characteristics of the controlled oscillator
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V_control. Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V_control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V_control. Accordingly, the magnitude of total control current is dominated by the transistor-provided component, and assumes a square relationship, with respect to the input control voltage. This square-law current-voltage gain characteristic compensates for the inversely mirrored frequency gain characteristic of the ring oscillator in order to attain a reduced frequency gain variation for the overall VCO, with respect to control voltage variations. This reduction in variation translates to a reduced variation in the frequency gain of the VCO with respect to temperature variations when the VCO is used in a phase locked loop (PLL) circuit.

Claims

1. A signal generator comprising:

means for generating an output signal having a value responsive to a control signal applied thereto; and

,

means for generating said control signal including means for modulating a control current signal between a first state and a second state as a function of an input signal, said control signal corresponding to said control current signal;

wherein when in said first state said modulating means is configured to increase said control current signal at a first rate substantially proportional to a rate of increase of said input signal, and when in said second state said modulating means is operable to increase said control current signal at a second rate that is substantially non-linear relative to said rate of increase of said input signal to thereby reduce a variation in a gain characteristic of said signal generator.

2. The generator of claim 1 wherein said second rate is substantially in accordance with the square of said rate of increase of said input signal.

3. The generator of claim 1 wherein said output signal generating means includes a plurality of stages connected in a series arrangement.

4. The generator of claim 3 wherein said output signal generating means includes a biasing circuit responsive to said control signal for driving said plurality of stages.

5. The generator of claim 1 wherein said control signal generating means includes a control transistor having a gate terminal biased by said input signal, and wherein said modulating means includes a passive device connected between said control transistor and a reference node, and an active device having a channel region connected between said control transistor and said reference node.

6. The generator of claim 5 wherein said passive device comprises a resistive element and wherein said active device is at least one field effect transistor (FET) configured to compensate for a current/frequency gain characteristic of said output signal generating means.

7. The generator of claim 6 wherein said one FET comprises an n-channel field effect transistor configured to operate substantially in saturation.

8. The generator of claim 7 wherein said modulating means further includes a p-channel field effect transistor having a channel region connected between said control transistor and said reference node, and configured to operate substantially in saturation.

9. The generator of claim 6 wherein said one FET comprises a p-channel field effect transistor configured to operate substantially in saturation.

10. The generator of claim 6 wherein said one FET comprises an n-channel field effect transistor having a gate terminal coupled to receive said input signal.

11. The generator of claim 10 wherein said modulating means further includes a p-channel field effect transistor having a channel region connected between said control transistor and said reference node, and further having a gate terminal coupled to receive said input signal.

12. The generator of claim 6 wherein said one FET comprises a p-channel field effect transistor having a gate terminal coupled to receive said input signal.

13. The generator of claim 1 wherein said control signal generating means includes a control transistor having a gate terminal biased by said input signal, and wherein said modulating means includes a first resistive element and a second resistive element sharing a first common node and together coupled in-series between said control transistor and a reference node, a third resistive element and a fourth resistive element sharing a second common node and together coupled in-series between said first common node and a distal node, an n-channel field effect transistor having a channel region coupled between said second common node and said reference node, and a p-channel field effect transistor having a channel region coupled between said distal node and said reference node wherein said n-channel field effect transistor and said p-channel field effect transistor being configured for operation in saturation.

14. A signal generator comprising:

an output circuit configured to generate an output signal having a value responsive to a control signal applied thereto;

a control circuit having an output for generating said control signal as a function of an input signal, said control circuit further including a control transistor having a first channel region for carrying a control current signal and a gate terminal coupled to receive said input signal, said control circuit further including a resistive element coupled between one end of said first channel and a reference node, said control circuit further including an active device having a second channel region coupled between said one end and said reference node;

wherein a magnitude of said control current signal comprises the sum of the respective currents through said resistive element and said active device as a function of said input signal.

15. The generator of claim 14 wherein said active device comprises an n-channel field effect transistor configured to operate in saturation, and a p-channel field effect transistor having a third channel region connected in parallel with said second channel region and configured to operate in saturation.

16. A method of operating a signal generator, said method comprising the steps of:

(A) generating an output signal having a value responsive to a biasing current signal;

(B) converting an input signal to a control current signal in a first state wherein a first rate of increase of said control current signal is substantially proportional to a rate of increase of said input signal; and

,

(C) converting said input signal to said control current signal in a second state wherein a second rate of increase of said control current signal is substantially non-linear relative to said rate of increase of said input signal to thereby reduce a variation in a gain characteristic of said generator.

17. The method of claim 16 wherein said second rate is substantially in accordance with the square of said rate of increase of said input signal.

18. The method of claim 17 wherein step (C) includes the substep of:

conducting said control current signal through at least one active device responsive to said input signal whose current/voltage characteristic is non-linear.