Drive circuit with reduced kickback voltage for liquid crystal display

• US 5,896,117 A
• Filed: 06/27/1996
• Issued: 04/20/1999
• Est. Priority Date: 09/29/1995
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Moon, Seung-Hwan
• Primary Examiner(s): LAO, LUNYI
• Application Number:
  US08/671,414
• Time in Patent Office: 1,027 Days
• Field of Search: 345/87, 345/91, 345/92, 345/94, 345/95, 345/204, 345/208, 345/210, 345/211, 345/212, 345/101, 349/41, 349/50, 349/43, 327/530
• US Class Current: 345/95
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A drive circuit and method for driving a thin film transistor liquid crystal display which reduce kickback voltage by generating a gate drive signal that has a reduced on voltage during a drop portion of the horizontal scanning time. The circuit includes a voltage signal generating circuit for receiving both a common electrode signal and an inverting common electrode signal and generating voltage signals, a drop signal generating circuit for generating drop signals, and a signal mixer circuit for combining the voltage signals and the drop signals and generating a composite output signal. The voltage signal generating circuit and the drop signal generating circuits both include a series of boost stages comprised of diode voltage multipliers. The signal mixing circuit includes a series of switches that are controlled by the drop signals. The length of the drop portion of the horizontal scan time can be controlled by a period control signal.

Claims

1. A drive circuit for an active liquid crystal display comprising:

voltage signal generating means for boosting a supply voltage signal to generate a voltage signal during a scanning time;

drop signal generating means for modifying the voltage signal during a portion of the scanning time to generate a drop signal; and

signal mixing means for combining the voltage signal and the drop signal to generate a composite signal.

2. A drive circuit according to claim 1 wherein the drop signal generating means includes a drop signal generator for receiving the voltage signal and generating a drop signal responsive to a control signal.

3. A drive circuit according to claim 1 wherein the signal mixing means includes a switch for receiving the voltage signal and generating the composite signal responsive to the drop signal.

4. A drive circuit according to claim 3 wherein the switch includes a transistor having a source terminal coupled to the voltage signal and a gate terminal coupled to the drop signal.

5. A drive circuit for an active liquid crystal display comprising:

voltage signal generating means for boosting a supply voltage signal to generate a voltage signal during a scanning time;

drop signal generating means for modifying the voltage signal during a portion of the scanning time to generate a drop signal; and

signal mixing means for combining the voltage signal and the drop signal to generate a composite signal;

wherein the voltage signal generating means includes a boost stage for receiving the supply voltage signal and generating the voltage signal responsive to an inverting common electrode signal.

6. A drive circuit according to claim 5 wherein the boost stage includes a diode and a capacitor, the anode of the diode coupled to the supply voltage signal, one terminal of the capacitor coupled to the cathode of the diode, the other terminal of the capacitor coupled to the inverting common electrode signal.

7. A drive circuit according to claim 5 wherein the voltage signal generating means further includes:

a second boost stage for receiving the voltage signal and generating a second voltage signal responsive to a common electrode signal;

a third boost stage for receiving the second voltage signal and generating a third voltage signal responsive to the inverting common electrode signal; and

a fourth boost stage for receiving the third voltage signal and generating a fourth voltage signal responsive to the common electrode signal.

8. A drive circuit according to claim 7 wherein:

the boost stage includes a diode and a capacitor, the anode of the diode coupled to the supply voltage signal, one terminal of the capacitor coupled to the cathode of the diode, the other terminal of the capacitor coupled to the inverting common electrode signal;

the second boost stage includes a second diode and a second capacitor, the anode of the second diode coupled to the voltage signal, one terminal of the second capacitor coupled to the cathode of the second diode, the other terminal of the second capacitor coupled to the common electrode signal;

the third boost stage includes a third diode and a third capacitor, the anode of the third diode coupled to the second voltage signal, one terminal of the third capacitor coupled to the cathode of the third diode, the other terminal of the third capacitor coupled to the inverting common electrode signal; and

the fourth boost stage includes a fourth diode and a fourth capacitor, the anode of the fourth diode coupled to the third voltage signal, one terminal of the fourth capacitor coupled to the cathode of the fourth diode, the other terminal of the fourth capacitor coupled to the common electrode signal.

9. A drive circuit for an active liquid crystal display comprising:

voltage signal generating means for boosting a supply voltage signal to generate a first voltage signal during a scanning time;

drop signal generating means for modifying the first voltage signal during a portion of the scanning time to generate a drop signal; and

signal mixing means for combining the first voltage signal and the drop signal to generate a composite signal;

wherein the drop signal generating means includes a drop signal generator for receiving the first voltage signal and generating a drop signal responsive to a control signal; and

wherein the drop signal generator includes a diode and a capacitor, the anode of the diode coupled to the first voltage signal, one terminal of the capacitor coupled to the cathode of the diode, the other terminal of the capacitor coupled to the control signal.

10. A drive circuit according to claim 9 wherein the drop signal generating means further includes:

a second drop signal generator for receiving the second voltage signal and generating a second drop signal responsive to the control signal, the second drop signal generator including a second diode and a second capacitor, the anode of the second diode coupled to the second voltage signal, one terminal of the second capacitor coupled to the cathode of the second diode, the other terminal of the second capacitor coupled to the control signal; and

a third drop signal generator for receiving the third voltage signal and generating a third drop signal responsive to the control signal, the third drop signal generator including a third diode and a third capacitor, the anode of the third diode coupled to the third voltage signal, one terminal of the third capacitor coupled to the cathode of the third diode, the other terminal of the third capacitor coupled to the control signal.

11. A drive circuit for an active liquid crystal display comprising:

voltage signal generating means for boosting a supply voltage signal to generate a first voltage signal during a scanning time;

drop signal generating means for modifying the first voltage signal during a portion of the scanning time to generate a drop signal; and

signal mixing means for combining the first voltage signal and the drop signal to generate a composite signal;

wherein the voltage signal generating means generates second, third and fourth voltage signals, the drop signal generating means generates first, second and third drop signals, and the signal mixing means includes;

a first switch for receiving the second voltage signal and generating a first portion of the composite signal responsive to the first drop signal;

a second switch for receiving the third voltage signal and generating a second portion of the composite signal responsive to the second drop signal;

a third switch for receiving the third voltage signal and generating a third portion of the composite signal responsive to the second drop signal; and

a fourth switch for receiving the fourth voltage signal and generating a fourth portion of the composite signal responsive to the third drop signal.

12. A drive circuit according to claim 11 wherein:

the first switch includes a transistor having a source terminal coupled to the second voltage signal and a gate terminal coupled to the first drop signal;

the second switch includes a transistor having a source terminal coupled to the third voltage signal and a gate terminal coupled to the second drop signal;

the third switch includes a transistor having a source terminal coupled to the third voltage signal and a gate terminal coupled to the second drop signal;

the fourth switch includes a transistor having a source terminal coupled to the fourth voltage signal and a gate terminal coupled to the third drop signal.

13. A drive circuit according to claim 11 further including a first diode having a cathode coupled to the second switch and a second diode having an anode coupled to the third switch, the anode of the first diode coupled to the cathode of the second diode.

14. A drive circuit for an active liquid crystal display comprising:

a voltage generating circuit having a supply terminal for receiving a supply signal, and a plurality of output terminals, the voltage generating circuit generating voltage signals at its output terminals;

a drop signal generating circuit having a plurality of input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, and a plurality of output terminals, the drop signal generating circuit modifying the voltage signals during a portion of a scanning time, thereby generating drop signals at its output terminals; and

a signal mixing circuit having a plurality of source input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, a plurality of gate input terminals coupled to the output terminals of the drop signal generating circuit to receive the drop signals, and an output terminal, the signal mixing circuit generating a composite signal at its output terminal.

15. A drive circuit for an active liquid crystal display comprising:

a voltage generating circuit having a supply terminal for receiving a supply signal, and a plurality of output terminals, the voltage generating circuit generating voltage signals at its output terminals;

a drop signal generating circuit having a plurality of input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, and a plurality of output terminals, the drop signal generating circuit generating drop signals at its output terminals; and

a signal mixing circuit having a plurality of source input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, a plurality of gate input terminals coupled to the output terminals of the drop signal generating circuit to receive the drop signals, and an output terminal, the signal mixing circuit generating a composite signal at its output terminal;

wherein the voltage generating circuit further includes;

an electrode terminal for receiving an electrode signal;

an inverting electrode terminal for receiving an inverting electrode signal;

a first diode having an anode coupled to the supply terminal and a cathode coupled to a first output terminal;

a second diode having an anode coupled to the first output terminal and a cathode coupled to a second voltage output terminal;

a third diode having an anode coupled to the second output terminal and a cathode coupled to a third output terminal;

a fourth diode having an anode coupled to the third output terminal and a cathode coupled to a fourth output terminal;

a first capacitor having a first terminal coupled to the cathode of the first diode and a second terminal coupled to the inverting electrode terminal;

a second capacitor having a first terminal coupled to the cathode of the second diode and a second terminal coupled to the electrode terminal;

a third capacitor having a first terminal coupled to the cathode of the third diode and a second terminal coupled to the inverting electrode terminal; and

a fourth capacitor having a first terminal coupled to the cathode of the fourth diode and a second terminal coupled to the electrode terminal.

16. A drive circuit for an active liquid crystal display comprising:

a voltage generating circuit having a supply terminal for receiving a supply signal, and a plurality of output terminals, the voltage generating circuit generating voltage signals at its output terminals;

a drop signal generating circuit having a plurality of input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, and a plurality of output terminals, the drop signal generating circuit generating drop signals at its output terminals; and

a signal mixing circuit having a plurality of source input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, a plurality of gate input terminals coupled to the output terminals of the drop signal generating circuit to receive the drop signals, and an output terminal, the signal mixing circuit generating a composite signal at its output terminal;

wherein the drop signal generating circuit further includes;

a control terminal for receiving a control signal;

a first diode having an anode coupled to a first input terminal and a cathode coupled to a first output terminal;

a second diode having an anode coupled to a second input terminal and a cathode coupled to a second output terminal;

a third diode having an anode coupled to a third input terminal and a cathode coupled to a third output terminal;

a first capacitor having a first terminal coupled to the cathode of the first diode and a second terminal coupled to the control terminal;

a second capacitor having a first terminal coupled to the cathode of the second diode and a second terminal coupled to the control terminal; and

a third capacitor having a first terminal coupled to the cathode of the third diode and a second terminal coupled to the control terminal.

17. A drive circuit for an active liquid crystal display comprising:

a voltage generating circuit having a supply terminal for receiving a supply signal, and a plurality of output terminals, the voltage generating circuit generating voltage signals at its output terminals;

a drop signal generating circuit having a plurality of input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, and a plurality of output terminals, the drop signal generating circuit generating drop signals at its output terminals; and

a signal mixing circuit having a plurality of source input terminals coupled to the output terminals of the voltage generating circuit to receive the voltage signals, a plurality of gate input terminals coupled to the output terminals of the drop signal generating circuit to receive the drop signals, and an output terminal, the signal mixing circuit generating a composite signal at its output terminal;

wherein the signal mixing circuit further includes;

a first transistor having a source coupled to a first source input terminal, a gate coupled to a first gate input terminal, and a drain coupled to the output terminal;

a second transistor having a source coupled to a second source input terminal, and a gate coupled to a second gate input terminal;

a third transistor having a source coupled to the second source input terminal, and a gate coupled to the second gate input terminal;

a fourth transistor having a source coupled to a third source input terminal, a gate coupled to a third gate input terminal, and a drain coupled to the output terminal;

a first diode having a cathode coupled to the drain of the second transistor and an anode coupled to the output terminal; and

a second diode having an anode coupled to the drain of the third transistor and a cathode coupled to the output terminal.