Low power parallel correlator for measuring correlation between digital signal segments

• US 5,896,304 A
• Filed: 06/26/1997
• Issued: 04/20/1999
• Est. Priority Date: 07/12/1996
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Harrison, Daniel David, Tiemann, Jerome Johnson
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/883,161
• Time in Patent Office: 663 Days
• Field of Search: 364/728.03-728.07, 364/604, 364/819, 375/208-210, 375/343
• US Class Current: 708/5
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G01S 19/42 Determining position
• CPC Class Codes: G01S 5/0027 of actual mobile position, i.e. position determined on mobile
• CPC Class Codes: G01S 5/0036 of measured values, i.e. measurement on mobile and position calculation on base station
• CPC Class Codes: G01S 5/0054 of actual mobile position, i.e. position calculation on base station
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 1/71075 Parallel interference cancellation
• CPC Class Codes: H04B 2201/70709 with discontinuous detection
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Correlation between a pair of digital signal segments is measured by apparatus including a plurality of multipliers. Each of the multipliers produces the product of a respective sample of each one of the signal segments. The outputs of a plurality of digital-to-analog (D/A) converters are coupled to a summer, while each respective one of the multipliers is coupled to the input of a respective one of the D/A converts. The summer produces an analog output signal equal to the sum of the analog output signals produced by the plurality of D/A converter.

Claims

1. A plural sequence parallel correlator comprising:

a plurality of multipliers, each of said multipliers being adapted to produce the product of a respective sample of each of a plurality of digital signal sequences;

a plurality of digital-to-analog (D/A) converters, each of said D/A converters being coupled to a respective one of said multipliers for converting the product produced by said respective one of said multipliers to an analog signal; and

a summer coupled to each of said D/A converters for summing the analog signals produced by said plurality of D/A converters.

2. The apparatus of claim 1 including a plurality of registers, each of said registers having a plurality of stages and being adapted to store a respective one of a plurality of digital signal sequences, each respective one of said multipliers being coupled to a respective stage of at least two of said plurality of registers.

3. The apparatus of claim 2 wherein at least one of said plurality of registers comprises a shift register.

4. The apparatus of claim 2 including a scanner shift register for scan loading at least one of said plurality of registers.

5. The apparatus of claim 1 wherein each of said D/A converters comprises at least one capacitor for storing a charge value corresponding to an associated digital representation of the product produced by said respective one of said multipliers, and wherein the analog summer comprises an electrical conductor coupled to the capacitors of all of said D/A converters for charge summation.

6. An apparatus for measuring correlation between first and second digital signals segments, said apparatus comprising:

a plurality of multipliers, each of said multipliers being s adapted to produce the product of a respective sample of each of said first and second segments;

a plurality of digital-to-analog (D/A) converters, each of said D/A converters being coupled to a respective one of said multipliers for converting the product produced by said respective one of said multipliers to an analog signal; and

a summer coupled to each of said D/A converters for summing the analog signals produced by said plurality of D/A converters.

7. The apparatus of claim 6 including a first register having a plurality of stages for storing said first digital signal segment, and a second register having a plurality of stages for storing said second digital segment, each respective one of said multipliers being coupled to a respective stage of said first register and to a respective stage of said second register.

8. The apparatus of claim 7 wherein one of said first and second registers comprises a shift register.

9. The apparatus of claim 8 including a scanner shift register for scan loading at least one of the first and second registers.

10. The apparatus of claim 6 wherein each of said D/A converters comprises at least one capacitor for storing a charge value corresponding to an associated digital representation of the product produced by said respective one of said multipliers, and wherein the analog summer comprises an electrical conductor coupled to the capacitors of all of said D/A converters for charge summation.