Data output control circuit for semiconductor memory device
First Claim
1. A data output control circuit for use in a semiconductor memory device, wherein input data is transmitted sequentially via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operation device, the data output buffer comprising:
- an output control circuit that combines the address transition detecting signal, a control signal, and the input data to output first and second signals, wherein the output control circuit comprises,a first logic circuit that receives a first of the two input data, the address transition detecting signal and the control signal to output an intermediate control signal,a second logic circuit that receives the second of the two input data, the address transition detecting signal and the control signal to output the second signal,a high signal output circuit that receives the intermediate control signal to output a high level first signal, anda low signal output circuit that receives the second input data, the address transition detecting signal and the control signal to output a low level first signal.
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Accused Products
Abstract
A data output control circuit for a semiconductor memory device sequentially transmits input data via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operator. The data output control circuit prevents false data output, which also improves data processing speed by using a control signal. The data output control circuit includes an output control unit that converts an address transition detecting signal into a kill signal. The kill signal is applied to the data output buffer to cause the output operator to generate a zero level signal based on the address transition detecting signal. The data output control circuit enables the output operator to generate a zero level signal by applying the kill signal to the data output buffer when the transition of an address signal is detected. Accordingly, an interval for a data reversal or a full swing is prevented to enhance data processing speed and reduce current consumption.
3 Citations
19 Claims
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1. A data output control circuit for use in a semiconductor memory device, wherein input data is transmitted sequentially via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operation device, the data output buffer comprising:
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an output control circuit that combines the address transition detecting signal, a control signal, and the input data to output first and second signals, wherein the output control circuit comprises, a first logic circuit that receives a first of the two input data, the address transition detecting signal and the control signal to output an intermediate control signal, a second logic circuit that receives the second of the two input data, the address transition detecting signal and the control signal to output the second signal, a high signal output circuit that receives the intermediate control signal to output a high level first signal, and a low signal output circuit that receives the second input data, the address transition detecting signal and the control signal to output a low level first signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A data output control circuit for a semiconductor memory device, comprising:
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a main amplifier that receives an address transition detecting signal for outputting data; a latch unit that latches the data received from the main amplifier; a data output buffer that combines the latched data from the latch unit, a control signal and the address transition detecting signal to output first and second signals; and an output device that receives the first and second signals from the data output buffer to output one of two level data in a data output state and a third signal different from each of the two level data in a suspended state. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A data output control circuit for a semiconductor memory device, comprising:
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a main amplifier responsive to an address transition detecting signal to output data; a latch unit that latches the data received from the main amplifier; a data output buffer that combines the latched data from the latch unit, a control signal and the address transition detecting signal to output first and second signals, wherein the data output buffer operates in first and second states, wherein in the first state the first and second signals are data signals, and wherein in the second state the first and second signals are non-data signals; and an output device that receives the first and second signals from the data output buffer to output one of the two level data signals and a third signal different from each of the two level data.
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Specification