Multi-port random access memory with shadow write test mode
First Claim
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1. A multi-port RAM (random access memory) comprising:
- RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells being coupled to respective row and column lines of each port, m and n being integers;
data write means for storing single-ended binary data in the RAM cells selected by signals on the row and column lines of a port;
data read means for reading the single-ended binary data stored in the RAM cells selected by signals on the row and column lines of a port; and
voltage driving means for applying a predetermined level voltage onto selected ones of the column lines in a shadow write mode.
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Abstract
Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
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11 Claims
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1. A multi-port RAM (random access memory) comprising:
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RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells being coupled to respective row and column lines of each port, m and n being integers; data write means for storing single-ended binary data in the RAM cells selected by signals on the row and column lines of a port; data read means for reading the single-ended binary data stored in the RAM cells selected by signals on the row and column lines of a port; and voltage driving means for applying a predetermined level voltage onto selected ones of the column lines in a shadow write mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification