Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same
First Claim
1. A semiconductor memory system comprising:
- at least one semiconductor memory device; and
a control device for inputting and outputting data from and to said semiconductor memory device,said control device outputting the data to said semiconductor memory device, synchronously with a first synchronizing signal that said control device outputs,said semiconductor memory device outputting the data to said control device synchronously with a second synchronizing signal that said semiconductor memory device outputs, andsaid semiconductor memory device including an output phase shift circuit for keeping a prescribed phase angle between the data from the semiconductor memory device and said second synchronizing signal.
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Accused Products
Abstract
A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs. In the thus constructed semiconductor memory system, the semiconductor memory device incorporates an output phase shift circuit which introduces a prescribed phase angle between the output data and second synchronizing signal, and provisions are made so that at the semiconductor memory device side the output data and the second synchronizing signal are controlled precisely at the prescribed phase angle with respect to each other, and so that a latch pulse can be immediately generated at the controller side upon reception of a data strobe signal.
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Citations
21 Claims
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1. A semiconductor memory system comprising:
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at least one semiconductor memory device; and a control device for inputting and outputting data from and to said semiconductor memory device, said control device outputting the data to said semiconductor memory device, synchronously with a first synchronizing signal that said control device outputs, said semiconductor memory device outputting the data to said control device synchronously with a second synchronizing signal that said semiconductor memory device outputs, and said semiconductor memory device including an output phase shift circuit for keeping a prescribed phase angle between the data from the semiconductor memory device and said second synchronizing signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor memory device, comprising:
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a data output circuit for outputting data synchronously with a basic output synchronizing signal; an output phase shift circuit for generating a shifted output synchronizing signal having a prescribed phase angle against said basic output synchronizing signal; and an output synchronizing signal output circuit for outputting said shifted output synchronizing signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification