System and method for encoding instruction fields within data packets

• US 5,896,383 A
• Filed: 05/01/1997
• Issued: 04/20/1999
• Est. Priority Date: 05/01/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wakeland, Carl
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): VANDERPUYE, KENNETH N
• Application Number:
  US08/845,640
• Time in Patent Office: 719 Days
• Field of Search: 370/466, 370/469, 370/392, 370/401, 370/402, 370/403, 370/474, 370/476, 370/410, 370/465, 370/471, 370/400, 370/522, 395/849, 395/858
• US Class Current: 370/400
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A communication system which includes more efficient packet conversion and routing for improved performance and simplified operation. The present invention includes an improved method for converting data packets between a plurality of different packet formats using a pre-defined generic packet format for simplified conversions. In order to perform a packet conversion, the method first converts a data packet having a first packet format to a the pre-defined generic packet format. The method then converts the data packet having the predefined generic packet format to a desired second different packet format. The method is thus operable to convert a data packet having any of a plurality of possible packet format types to the pre-defined generic packet format, and to convert a data packet having the pre-defined generic packet format to a data packet having any of the plurality of possible packet format types. The present invention also includes a system comprising a plurality of processors which operate to exchange packets in a common format, such as the generic format described above. In this embodiment, the system includes an instruction field comprising instructions within each of the data packets to produce instruction encoded packets. Each of the plurality of processors operate to exchange the instruction encoded packets in the common format. Each of the plurality of processors are operable to include instructions in an instruction field of a packet and to execute instructions from the instruction field comprised in the instruction encoded packets. The instructions may direct a processor to perform operations on data comprised in the instruction encoded packets or perform routing operations on the instruction encoded packets.

Claims

1. A system for manipulating data packets comprising:

logic adapted to receive one or more input data packets, wherein the logic is operable to include a non-routing instruction field comprising non-routing instructions within the one or more input data packets to produce instruction encoded packets, wherein said instruction encoded packets include said non-routing instruction field comprising non-routing instructions and a data field comprising data;

a data bus for communicating data;

one or more processors coupled to the data bus, wherein said one or more processors comprise;

parsing logic including an input coupled to receive an instruction encoded packet, wherein said parsing logic operates to extract said non-routing instructions from said non-routing instruction field comprised in said instruction encoded packet and output said non-routing instructions;

an instruction buffer coupled to receive said non-routing instructions from said parsing logic;

a processor block coupled to the instruction buffer which is operable to read said non-routing instructions from said instruction buffer and execute said non-routing instructions to operate on said data comprised in said instruction encoded packet, and

wherein each of the one or more processors operate to exchange said instruction encoded packets,

wherein the one or more of the processors are operable to execute instructions from said instruction field comprised in said instruction encoded packets.

2. The system of claim 1, wherein the one or more processors are operable to execute instructions from said non-routing instruction field comprised in said instruction encoded packets to perform operations on data comprised in said instruction encoded packets.

3. The system of claim 1, wherein said instruction encoded packets have a common format, wherein said one or more processors comprise a plurality of processors, wherein each of the plurality of processors comprise an identical instruction set for operating on said instruction encoded packets.

4. The system of claim 1, wherein said one or more processors comprise a plurality of processors, wherein the logic operable to include said non-routing instruction field comprising said non-routing instructions within the one or more input data packets to produce instruction encoded packets comprises one or more of said plurality of processors.

5. The system of claim 4, wherein a first processor of said plurality of processor is operable to embed said non-routing instructions in one of said input data packets to produce said instruction encoded packets, wherein a second processor of said plurality of processors is operable to read said embedded non-routing instructions in said instruction encoded packets and to execute said non-routing instructions in said instruction encoded packets to perform operations on the packet data comprised in the instruction encoded packets.

6. The system of claim 1, wherein said one or more processors comprise a plurality of processors, wherein said data bus is configured in a ring topology;

wherein said instruction encoded packets travel on said data bus configured in said ring topology.

7. The system of claim 1, wherein said parsing logic further generates a strobe signal indicating the start of the non-routing instructions output from the parsing logic, wherein said strobe signal is provided to an input of said processor block, wherein said processor block is configured to read said non-routing instructions from said instruction buffer in response to receiving said strobe signal.

16. The system of claim 1, wherein the one or more processors are operable to execute instructions from said instruction field comprised in said instruction encoded packets to perform routing operations on said instruction encoded packets.

8. A system for manipulating data packets comprising:

a data bus for communicating data;

a plurality of processors coupled to the data bus, wherein at least one of the processors is operable to receive one or more input data packets, wherein the at least one of the processors is operable to include a non-routing instruction field comprising non-routing instructions within the one or more input data packets to produce instruction encoded packets, wherein said instruction encoded packets include a non-routing instruction field comprising non-routing instructions and a data field comprising data, wherein each of the plurality of processors are operable to exchange said instruction encoded packets, wherein each of the plurality of processors are operable to execute instructions from said non-routing instruction field comprised in said instruction encoded packets; and

wherein said plurality of processors each comprise;

parsing logic including an input coupled to receive an instruction encoded packet, wherein said parsing logic operates to extract said non-routing instructions from said non-routing instruction field comprised in said instruction encoded packet and output said non-routing instructions;

an instruction buffer coupled to receive said non-routing instructions from said parsing logic; and

a processor block coupled to the instruction buffer which is operable to read said non-routing instructions from said instruction buffer and execute said non-routing instructions to operate on said data comprised in said instruction encoded packet.

9. The system of claim 8, wherein the plurality of processors are operable to execute instructions from said non-routing instruction field comprised in said instruction encoded packets to perform operations on data comprised in said instruction encoded packets.

10. The system of claim 8, wherein said instruction encoded packets have a common format, wherein each of the plurality of processors comprise an identical instruction set for operating on said instruction encoded packets.

11. The system of claim 8, wherein the logic operable to include said non-routing instruction field comprising said non-routing instructions within the one or more input data packets to produce said instruction encoded packets comprises one or more of said plurality of processors.

12. The system of claim 11, wherein a first processor of said plurality of processors is operable to embed non-routing instructions in one of said input data packets to produce instruction encoded packets, wherein a second processor of said plurality of processors is operable to read said embedded non-routing instructions in said instruction encoded packets and to execute said non-routing instructions in said instruction encoded packets to perform operations on the packet data comprised in the instruction encoded packets.

13. The system of claim 8, wherein said data bus is configured in a ring topology;

wherein said instruction encoded packets travel on said data bus configured in said ring topology.

14. The system of claim 8, wherein said parsing logic further generates a strobe signal indicating the start of the instructions output from the parsing logic, wherein said strobe signal is provided to an input of said processor block, wherein said processor block is configured to read said non-routing instructions from said instruction buffer in response to receiving said strobe signal.

15. The system of claim 8, wherein said system comprises a router for routing data packets between networks.

17. The system of claim 8, wherein the plurality of processors are operable to execute instructions from said instruction field comprised in said instruction encoded packets to perform routing operations on said instruction encoded packets.

18. A system for manipulating data packets comprising:

logic adapted to receive one or more input data packets, wherein the logic is operable to include a non-routing instruction field comprising non-routing instructions within the one or more input data packets to produce instruction encoded packets, wherein said instruction encoded packets include said non-routing instruction field comprising non-routing instructions and a data field comprising data;

a data bus for communicating data;

one or more processors coupled to the data bus, wherein said one or more processors comprise;

parsing logic including an input coupled to receive an instruction encoded packet, wherein said parsing logic operates to extract said non-routing instructions from said non-routing instruction field comprised in said instruction encoded packet and output said non-routing instructions, wherein said parsing logic operates to extract said data from said data field comprised in said instruction encoded packet and output said instructions;

an instruction buffer coupled to receive said non-routing instructions from said parsing logic;

a processor block coupled to the instruction buffer which is operable to read said non-routing instructions from said instruction buffer and execute said non-routing instructions to operate on said data output from said parsing logic, and

wherein each of the one or more processors operate to exchange said instruction encoded packets,

wherein the one or more of the processors are operable to execute instructions from said instruction field comprised in said instruction encoded packets.

19. The system of claim 18, wherein the one or more processors are operable to execute instructions from said non-routing instruction field comprised in said instruction encoded packets to perform operations on data comprised in said instruction encoded packets.

20. The system of claim 18, wherein the one or more processors are operable to execute instructions from said instruction field comprised in said instruction encoded packets to perform routing operations on said instruction encoded packets.

21. The system of claim 18, wherein said instruction encoded packets have a common format, wherein said one or more processors comprise a plurality of processors, wherein each of the plurality of processors comprise an identical instruction set for operating onsaid instruction encoded packets.

22. The system of claim 18, wherein said one or more processors comprise a plurality of processors, wherein the logic operable to include said non-routing instruction field comprising said non-routing instructions within the one or more input data packets to produce instruction encoded packets comprises one or more of said plurality of processors.

23. The system of claim 22, wherein a first processor of said plurality of processor is operable to embed said non-routing instructions in one of said input data packets to produce said instruction encoded packets, wherein a second processor of said plurality of processors is operable to read said embedded non-routing instructions in said instruction encoded packets and to execute said non-routing instructions in said instruction encoded packets to perform operations on the packet data comprised in the instruction encoded packets.

24. The system of claim 18, wherein said one or more processors comprise a plurality of processors, wherein said data bus is configured in a ring topology;

wherein said instruction encoded packets travel on said data bus configured in said ring topology.

25. The system of claim 18, wherein said parsing logic further generates a strobe signal indicating the start of the non-routing instructions output from the parsing logic, wherein said strobe signal is provided to an input of said processor block, wherein said processor block is configured to read said non-routing instructions from said instruction buffer in response to receiving said strobe signal.