Loosely-coupled, synchronized execution

• US 5,896,523 A
• Filed: 06/04/1997
• Issued: 04/20/1999
• Est. Priority Date: 06/04/1997
• Status: Expired due to Term

• Current Assignee: Stratus Technologies Bermuda Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Marathon Technologies Corporation (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: Bissett, Thomas D., Leveille, Paul A., Muench, Erik, Tremblay, Glenn A.
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US08/868,670
• Time in Patent Office: 685 Days
• Field of Search: 395/388, 395/390, 395/551, 395/552, 395/553, 395/557, 395/559, 395/182.1
• US Class Current: 713/400
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/1691 using a quantum
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

Synchronized execution is maintained by compute elements processing instruction streams in a computer system including the compute elements and a controller. Each compute element includes a clock that operates asynchronously with respect to clocks of the other compute elements. Each compute element processes instructions from an instruction stream and counts the instructions processed. Upon processing a quantum of instructions from the instruction stream, the compute element initiates a synchronization procedure and continues to process instructions from the instruction stream and to count instructions processed from the instruction stream. The compute element halts processing of instructions from the instruction stream after processing an unspecified number of instructions from the instruction stream in addition to the quantum of instructions. Upon halting processing, the compute element sends a synchronization request to the controller and waits for a synchronization reply.

Claims

1. A method of maintaining synchronized execution by compute elements processing instruction streams in a computer system including the compute elements and a controller, wherein each compute element comprises a clock that operates asynchronously of clocks of the other compute elements, said method comprising at each compute element:

processing instructions from an instruction stream;

counting instructions processed from the instruction stream;

initiating a synchronization procedure upon processing a quantum of instructions from the instruction stream;

after initiating the synchronization procedure, continuing to process instructions from the instruction stream and to count instructions processed from the instruction stream;

halting processing of instructions from the instruction stream after processing an unspecified number of instructions from the instruction stream in addition to the quantum of instructions;

upon halting processing, sending a synchronization request to the controller; and

waiting for a synchronization reply from the controller.

2. The method of claim 1, wherein the continuing to process instructions from the instruction stream and to count instructions processed from the instruction stream comprises single-stepping through the instructions under control of the synchronization procedure.

3. The method of claim 2, wherein the continuing to process instructions comprises single-stepping through at least a specified number of instructions associated with permitted asynchronous activities of the compute element.

4. The method of claim 3, wherein each compute element comprises a processor and the specified number of instructions is determined empirically for a type associated with a compute element'"'"'s processor.

5. The method of claim 2, wherein, when an instruction disables interrupts, the continuing to process instructions from the instruction stream comprises processing the instructions at full speed until interrupts are re-enabled.

6. The method of claim 2, wherein, when an instruction comprises a repeat instruction, the continuing to process instructions from the instruction stream comprises processing the instructions at full speed until an instruction following the repeat instruction is encountered.

7. The method of claim 1, further comprising, upon receiving the synchronization reply, repeating the processing, counting and initiating.

8. The method of claim 1, wherein the unspecified number of instructions is greater than or equal to a specified number of instructions associated with permitted asynchronous activities of the compute element.

9. The method of claim 8, wherein the permitted asynchronous activities comprise at least one of background DMA, memory refresh, cache fills and writebacks, branch prediction, instruction prefetch, and data prefetch.

10. The method of claim 1, wherein the initiating the synchronization procedure comprises generating an interrupt that calls the synchronization procedure.

11. The method of claim 10, wherein the generating the interrupt comprises generating the interrupt when a performance counter of the compute element indicates that the quantum of instructions have been processed.

12. The method of claim 11, further comprising disabling the performance counter when processing instructions other than instructions from the instruction stream.

13. The method of claim 12, wherein the instructions other than instructions from the instruction stream comprise instructions of the synchronization procedure.

14. The method of claim 10, wherein continuing to process instructions from the instruction stream comprises continuing to process instructions from the instruction stream after receiving the interrupt generated to call the synchronization procedure.

15. The method of claim 1, wherein the synchronization request comprises information about the state of the compute element, the method further comprising, at the controller:

receiving synchronization requests from each compute element;

cross-checking for consistency information from the synchronization requests about the states of the compute elements; and

sending the synchronization reply upon determining that the states of the compute elements are consistent.

16. The method of claim 15, further comprising activating a fault handler upon determining that the states of the compute elements are inconsistent.

17. The method of claim 15, further comprising including a time-of-day update in the synchronization reply.

18. The method of claim 17, further comprising, at the compute elements, receiving the synchronization reply and updating the clocks of the compute elements based on the time-of-day update from the synchronization reply.

19. The method of claim 1, further comprising, at the controller:

receiving synchronization requests from each compute element; and

sending the synchronization reply to the compute elements, the synchronization reply including a time-of-day update.

20. The method of claim 19, further comprising, at the compute elements, receiving the synchronization reply and updating the clocks of the compute elements based on the time-of-day update from the synchronization reply.

21. The method of claim 1, wherein a first compute element is separated from a second compute element by a distance of at least one hundred meters.

22. The method of claim 1, further comprising:

at the compute elements, when an instruction from the instruction stream requests information from an input/output device, redirecting the request to the controller; and

at the controller, receiving the redirected request from the compute elements, processing the request, and returning results of the request to the compute elements.

23. The method of claim 1, wherein each compute element comprises an Intel Pentium Pro processor.

24. The method of claim 1, wherein the stream of instructions is associated with application and operating system software.

25. The method of claim 24, wherein the operating system software comprises unmodified, Microsoft Windows NT operating system software.

26. A computer system including compute elements configured to process instruction streams and a controller, wherein;

the compute elements and the controller are configured to maintain synchronized execution by the compute elements;

each compute element comprises a clock that operates asynchronously of clocks of the other compute elements; and

each compute element is configured to;

process instructions from an instruction stream;

count instructions processed from the instruction stream;

initiate a synchronization procedure upon processing a quantum of instructions from the instruction stream;

continue to process instructions from the instruction stream and to count instructions processed from the instruction stream after initiating the synchronization procedure;

halt processing of instructions from the instruction stream after processing an unspecified number of instructions from the instruction stream in addition to the quantum of instructions;

send a synchronization request to the controller upon halting processing; and

wait for a synchronization reply from the controller.

27. The system of claim 26, continuing to process instructions from the instruction stream and to count instructions processed from the instruction stream comprises single-stepping through the instructions under control of the synchronization procedure.

28. The system of claim 27, wherein continuing to process instructions comprises single-stepping through at least a specified number of instructions associated with permitted asynchronous activities of the compute element.

29. The system of claim 28, wherein each compute element comprises a processor and the specified number of instructions is determined empirically for a type associated with a compute element'"'"'s processor.

30. The system of claim 27, wherein, when an instruction disables interrupts, continuing to process instructions from the instruction stream comprises processing the instructions at full speed until interrupts are re-enabled.

31. The system of claim 27, wherein, when an instruction comprises a repeat instruction, continuing to process instructions from the instruction stream comprises processing the instructions at full speed until an instruction following the repeat instruction is encountered.

32. The system of claim 26, wherein each compute element is further configured to, upon receiving the synchronization reply, repeat the processing, counting and initiating.

33. The system of claim 26, wherein the unspecified number of instructions is greater than or equal to a specified number of instructions associated with permitted asynchronous activities of the compute element.

34. The system of claim 33, wherein the permitted asynchronous activities comprise at least one of background DMA, memory refresh, cache fills and writebacks, branch prediction, instruction prefetch, and data prefetch.

35. The system of claim 26, wherein each compute element is configured to initiate the synchronization procedure by generating an interrupt that calls the synchronization procedure.

36. The system of claim 35, wherein each compute element is configured to generate the interrupt by generating the interrupt when a performance counter of the compute element indicates that the quantum of instructions have been processed.

37. The system of claim 36, wherein each compute element is configured to disable the performance counter when processing instructions other than instructions from the instruction stream.

38. The system of claim 35, wherein each compute element is configured to continue to process instructions from the instruction stream after receiving the interrupt generated to call the synchronization procedure.

39. The system of claim 26, wherein:

the synchronization request comprises information about the state of the compute element; and

the controller is configured to;

receive synchronization requests from each compute element;

cross-check for consistency information from the synchronization requests about the states of the compute elements; and

send the synchronization reply upon determining that the states of the compute elements are consistent.

40. The system of claim 39, wherein the controller is configured to activate a fault handler upon determining that the states of the compute elements are inconsistent.

41. The system of claim 39, wherein the controller is configured to include a time-of-day update in the synchronization reply.

42. The system of claim 41, wherein each compute element is configured to receive the synchronization reply and update the clock of the compute element based on the time-of-day update from the synchronization reply.

43. The system of claim 26, wherein the controller is configured to receive synchronization requests from each compute element and send the synchronization reply to the compute elements, with the synchronization reply including a time-of-day update.

44. The system of claim 43, wherein each compute element is configured to receive the synchronization reply and update the clock of the compute element based on the time-of-day update from the synchronization reply.

45. The system of claim 26, wherein a first compute element is separated from a second compute element by a distance of at least one hundred meters.

46. The system of claim 26, wherein each compute element is configured to redirect a request to the controller when an instruction from the instruction stream requests information from an input/output device, and the controller is configured to receive the redirected requests from the compute elements, process the requests, and return results of the request to the compute elements.

47. The system of claim 26, wherein each compute element comprises an Intel Pentium Pro processor.