Programmable instruction trap system and method

• US 5,896,526 A
• Filed: 02/18/1998
• Issued: 04/20/1999
• Est. Priority Date: 06/01/1995
• Status: Expired due to Term

• Current Assignee: HAL Computer Systems, Inc. (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Sajjadian, Farnad, Shen, Gene W., Savkar, Sunil, Shebanow, Michael C.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US09/025,511
• Time in Patent Office: 426 Days
• Field of Search: 395/183.1, 395/183.11, 395/183.14, 395/568, 395/591, 395/739
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A system and method providing a programmable hardware device within a CPU. The programmable hardware device permits a plurality of instructions to be trapped before they are executed. The instructions that are to be trapped are programmable to provide flexibility during CPU debugging and to ensure that a variety of application programs can be properly executed by the CPU. The system must also provide a means for permitting a trapped instruction to be emulated and/or to be executed serially. Related Applications

Claims

1. Microprocessor, comprising:

an instruction fetch unit, disposed to receive a plurality of computer instructions, for retrieving said plurality of computer instructions; and

a programmable instruction trap unit, coupled to said fetch unit, for comparing each of said computer instructions with one of a plurality of programmable values, and for generating an instruction trap control signal for each of said instructions representing a function to be performed for each of said computer instructions in response to said comparisons, said programmable instruction trap unit including;

a plurality of first programmable registers, each of said first programmable registers for automatically receiving and storing a first value representing one or more trap instructions that a user wants to trap, said first value is programmable by said user;

a plurality of first comparators, each disposed to receive one of said computer instructions and one of said programmable register values, for determining if said computer instruction matches said programmable register value;

a plurality of programmable control registers, each of said programmable control registers associated with one of said first programmable registers, for storing a second value representing a function to be performed if said first comparator determines said computer instruction matches said programmable register value; and

a plurality of control units, each coupled to said programmable control registers for generating a plurality of signals representing said second value if one of said first programmable registers matches one of said computer instructions.

2. The microprocessor of claim 1, wherein each of said first comparators comprises:

a second comparator, disposed to receive said computer instruction; and

a third comparator, coupled to said control unit and disposed to receive an output of said second comparator.

3. The microprocessor of claim 2, wherein each of said first programmable registers includes:

a value register, coupled to said second comparator, for storing data representing one or more of said trap instructions;

a mask register coupled to said third comparator, for storing mask information associated with said value register, each bit of said mask information represents one of a mask bit indicator and a don'"'"'t mask bit indicator.

4. The microprocessor of claim 3, wherein said second comparator compares each bit of said computer instruction with an associated bit of said value register and generates a first bit value representing the second comparator result.

5. The microprocessor of claim 4, wherein said third comparator compares each first bit value output with an associated bit from said mask register and generates a second bit value representing the third comparator result.

6. The microprocessor of claim 4, wherein said third comparator compares all of said first bit values output by said second comparator with all associated bits of said mask register and generates matching signal if all bit comparisons match.

7. The microprocessor of claim 2, wherein four instructions are simultaneously compared with all of said first programmable registers.

20. The microprocessor of claim 1, further including:

an issue unit, coupled to said programmable instruction trap unit, for receiving said instruction trap control signal, said issue unit executing said function in an asynchronous manner.

8. A method for identifying computer program instructions in a microprocessor comprising a plurality of first registers, second registers, and control registers, comprising the steps of:

programming all bits in said plurality of first registers, said plurality of second registers, and said plurality of control registers;

receiving a plurality of instructions having a plurality of bits;

performing a first comparison of each bit of each instruction with an associated bit of each of said first registers;

generating a first bit value for each of said first comparisons;

performing a second comparison of each of said first bit values with an associated bit of said second register that is associated with said first bit value; and

generating a signal representing the contents of an associated control register if said instruction satisfies said second comparison.

9. The method of claim 8 wherein each of said plurality of first registers store a first computer program instruction representation.

10. The method of claim 8 wherein each of said plurality of second registers store mask bits for identifying bits of said instruction that are relevant for said second comparison.

11. The method of claim 8 wherein each of said plurality of control registers identifies a location in a memory device at which an alternate computer program is stored that corresponds to the action to be taken if said instruction matches said second comparison.

12. The method of claim 8, wherein said step of programming all bits in said plurality of first registers, said plurality of second registers, and said plurality of control registers includes the step of:

scanning in all of the values for said first registers, said second registers, and said control registers.

13. The method of claim 12, wherein said scanning step includes the step of:

sequentially receiving binary values and storing the values in said first registers, second registers, and control registers.

14. A microprocessor for identifying computer program instructions comprising:

a plurality of first registers;

a plurality of second registers;

a plurality of control registers,

programming means for programming all bits in said plurality of first registers, said plurality of second registers, and said plurality of control registers;

instruction receiving means for receiving a plurality of instructions having a plurality of bits;

first comparison means, coupled to said first registers and said instruction receiving means, for performing a first comparison of each bit of each instruction with an associated bit of each of said first registers;

first generation means, coupled to said first comparison means, for generating a first bit value for each of said first comparisons;

second comparison means, coupled to said first generation means, for performing a second comparison of each of said first bit values with an associated bit of said second register that is associated with said first bit value; and

second generation means, coupled to said second comparison means, for generating a signal representing the contents of an associated control register if said instruction satisfies said second comparison.

15. The microprocessor of claim 14 wherein each of said plurality of first registers store a first computer program instruction representation.

16. The microprocessor of claim 14 wherein each of said plurality of second registers store mask bits for identifying bits of said instruction that are relevant for said second comparison.

17. The microprocessor of claim 14 wherein each of said plurality of control registers identifies a location in a memory device at which an alternate computer program is stored that corresponds to the action to be taken if said instruction matches said second comparison.

18. The microprocessor of claim 14, wherein said step of programming all bits in said plurality of first registers, said plurality of second registers, and said plurality of control registers includes the step of:

scanning in all of the values for said first registers, said second registers, and said control registers.

19. The microprocessor of claim 18, wherein said scanning step includes the step of:

sequentially receiving binary values and storing the values in said first registers, second registers, and control registers.

21. A computer processing system capable of executing computer instructions asynchronously, comprising:

an instruction fetch unit, disposed to receive a plurality of computer instructions, for retrieving said plurality of computer instructions; and

a programmable instruction trap unit, coupled to said fetch unit, for comparing each of said computer instructions with one of a plurality of programmable values, and for generating an instruction trap control signal for each of said instructions representing an emulation routine to be performed instead of said computer instructions in response to said comparisons, said programmable instruction trap unit including;

a plurality of first programmable registers, each of said first programmable registers for storing a first value representing one or more trap instructions that a user wants to trap, said first value is programmable by said user;

a plurality of first comparators, each disposed to receive one of said computer instructions and one of said programmable register values, for determining if said computer instruction matches said programmable register value;

a plurality of programmable control registers, each of said programmable control registers associated with one of said first programmable registers, for storing a second value representing a trap synchronizing function to be performed if said first comparator determines said computer instruction matches said programmable register value; and

a plurality of control units, each coupled to said programmable control registers, for generating a plurality of signals representing said second value if one of said first programmable registers matches one of said computer instructions.

22. The computer processing system of claim 21, wherein each of said first comparators comprises:

a second comparator, disposed to receive said computer instruction; and

a third comparator, coupled to said control unit and disposed to receive an output of said second comparator.

23. The computer processing system of claim 21, wherein each of said first programmable registers includes:

a value register, coupled to said second comparator, for storing data representing one or more of said trap instructions;

a mask register coupled to said third comparator, for storing mask information associated with said value register, each bit of said mask information represents one of a mask bit indicator and a don'"'"'t mask bit indicator.

24. The computer processing system of claim 23, wherein said second comparator compares each bit of said computer instruction with an associated bit of said value register and generates a first bit value representing the second comparator result.

25. The computer processing system of claim 24, wherein said third comparator compares each first bit value output with an associated bit from said mask register and generates a second bit value representing the third comparator result.