Digital signal processor architecture

• US 5,896,543 A
• Filed: 01/25/1996
• Issued: 04/20/1999
• Est. Priority Date: 01/25/1996
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Garde, Douglas
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): FOLLANSBEE, JOHN A
• Application Number:
  US08/591,135
• Time in Patent Office: 1,181 Days
• Field of Search: 395/800.1, 395/800.09, 395/800.32, 395/800.35, 395/376, 395/380, 395/382, 395/391, 395/394, 395/563, 395/800.02, 364/716.07, 364/736.04, 364/748.01, 364/748.13, 364/748.19
• US Class Current: 712/35
• CPC Class Codes: G06F 15/7857 using interleaved memory addressing G06F12/0607
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3552 using wraparound, e.g. modulo or circular addressing
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3875 Pipelining a single stage, e.g. superpipelining
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.

Claims

1. A digital signal processor comprising:

a memory for storing instructions and operands for digital signal computations;

a core processor connected to said memory, said core processor comprising;

a program sequencer for generating instruction addresses for fetching selected ones of said instructions from said memory;

a first computation block for performing a first subset of said digital signal computations under control of said program sequencer using a first subset of said instructions and a first subset of said operands; and

a second computation block for performing a second subset of said digital signal computations under control of said program sequencer using a second subset of said instructions and a second subset of said operands, said first and second computation blocks each comprising a register file for temporary storage of operands and results, a multiplier for performing multiplication operations, an ALU for performing arithmetic operations and a shifter for performing shifting operations; and

means for transferring said first subset of said instructions and said first subset of said operands from said memory to said first computation block for execution and for transferring said second subset of said instructions and said second subset of said operands from said memory to said second computation block for execution, wherein said first and second computation blocks share said memory.

2. A digital signal processor as defined in claim 1 wherein each of said first and second computation blocks includes means for executing plural instructions during each clock cycle.

3. A digital signal processor as defined in claim 1 wherein said multiplier includes means for selectably executing 32-bit by 32-bit multiplication instructions or quad 16-bit by 16-bit multiplication instructions.

4. A digital signal processor as defined in claim 1 wherein the register file in each of said first and second computation blocks includes means for storing multiple operands during each clock cycle and means for writing multiple operands to said memory during each clock cycle.

5. A digital signal processor as defined in claim 1 wherein said register file, said multiplier, said ALU and said shifter are interconnected by a plurality of register file output buses and by a plurality of result buses.

6. A digital signal processor as defined in claim 5 wherein said multiplier, said ALU and said shifter each include means for selecting inputs from said result buses, whereby intermediate operands are obtained without first being stored in said register file.

7. A digital signal processor as defined in claim 1 wherein said memory comprises a first memory bank for storing said instructions and second and third memory banks for storing said operands, and wherein said core processor further includes transfer selection means responsive to said instructions for selectably transferring plural operands from each of said second and third memory banks during each clock cycle and providing said plural operands to one or both of said first and second computation blocks for performing said digital signal computations.

8. A digital signal processor as defined in claim 7 wherein said transfer selection means includes means for selectably transferring single, dual or quad operands from each of said second and third memory banks to one or both of said first and second computation blocks during each clock cycle.

9. A digital signal processor as defined in claim 8 wherein said transfer selection means includes means for writing results of said digital signal computations from one or both of said first and second computation blocks to said second and third memory banks during each clock cycle.

10. A digital signal processor as defined in claim 7 wherein said transfer selection means includes means for transferring plural instructions from said first memory bank to one or both of said first and second computation blocks during each clock cycle.

11. A digital signal processor as defined in claim 7 wherein said core processor further includes a first data address generator for generating addresses for fetching operands from said second memory bank and a second data address generator for generating addresses for fetching operands from said third memory bank.

12. A digital signal processor as defined in claim 11 wherein said first and second data address generators also function as integer arithmetic logic units for executing integer ALU instructions.

13. A digital signal processor as defined in claim 11 wherein said first and second data address generators each include circular buffer registers for identifying a base and a length of a buffer being accessed by each of said data address generators.

14. A digital signal processor as defined in claim 7 wherein said transfer selection means includes means for transferring up to four operands of 32 bits each from each of said second and third memory banks to one or both of said first and second computation blocks during each clock cycle.

15. A digital signal processor as defined in claim 7 wherein each of said first, second and third memory banks is organized as quad word rows and wherein said transfer selection means includes means for selectively accessing single, dual or quad operands in the quad word rows of said second and third memory banks during each clock cycle.

16. A digital signal processor as defined in claim 15 wherein said first and second computation blocks each include means for writing results of digital signal computations to different words of a selected quad word row in said memory during each clock cycle.

17. A digital signal processor as defined in claim 7 further including first data and address buses interconnecting said core processor and said first memory bank, second data and address buses interconnecting said core processor and said second memory bank, and third data and address buses interconnecting said core processor and said third memory bank.

18. A digital signal processor as defined in claim 7 wherein each of said second and third memory banks is organized as quad word rows and wherein said transfer selection means includes means for selectively addressing single, dual or quad locations in each of said second and third memory banks, and means for selectively transferring operands from said single, dual or quad locations to one or both of said first and second computation blocks during each clock cycle.

19. A digital signal processor as defined in claim 1 wherein said core processor further includes an instruction alignment buffer for aligning instructions that are read from said memory on different clock cycles but are required to be executed in one clock cycle.

20. A digital signal processor as defined in claim 1 wherein said means for transferring includes means for transferring said instructions and operands from said memory to one or both of said first and second computation blocks during each clock cycle.

21. A digital signal processor as defined in claim 1 wherein said first and second subsets of said instructions are the same.

22. A digital signal processor as defined in claim 1 wherein said first and second subsets of said instructions are different.

23. A method for digital signal processing comprising the steps of:

storing instructions and operands for digital signal computations in a memory;

in a program sequencer, generating instruction addresses for fetching selected ones of the instructions from the memory;

in a first computation block comprising a register file for temporary storage of operands and results, a multiplier for performing multiplication operations, an ALU for performing arithmetic operations and a shifter for performing shifting operations, performing a first subset of the digital signal computations under control of the program sequencer using a first subset of the instructions and a first subset of the operands;

in a second computation block comprising a register file for temporary storage of operands and results, a multiplier for performing multiplication operations, an ALU for performing arithmetic operations and a shifter for performing shifting operations, performing a second subset of the digital signal computations under control of the program sequencer using a second subset of the instructions and a second subset of the operands; and

transferring the first subset of the instructions and the first subset of the operands from the memory to the first computation block for execution and transferring the second subset of the instructions and the second subset of the operands from the memory to the second computation block for execution, wherein said first and second computation blocks share said memory.