Method of making a power switching trench MOSFET having aligned source regions

• US 5,897,343 A
• Filed: 03/30/1998
• Issued: 04/27/1999
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Mathew, Leo, Tran, Huy Trong, Venkatraman, Prasad, Nguyen, Bich-Yen, Pearse, Jeffrey, Kamekona, Keith G.
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US09/050,164
• Time in Patent Office: 393 Days
• Field of Search: 438/133, 438/135, 438/136, 438/137, 438/138, 438/140, 438/268, 438/269, 438/270, 438/271
• US Class Current: 438/133
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench power switching transistor (10) is fabricated having sub-micron features on a body layer (26) without using sub-micron lithography. An opening in a field oxide layer (28) defines an area for implanting a source region (30) in the body layer (26) that is self-aligned to a first edge (28A) and a second edge (28B) of the field oxide layer (28). Sidewall spacers (32) are formed in accordance with the first and second edges (28A and 28B) of the field oxide layer (28). A trench is aligned to the sidewall spacers (32) and formed centered within the source region (30). An implant layer (42) formed between sections of the power switching transistor (10) is aligned to the sidewall spacers (32) at the first and second edges (28A and 28B).

Claims

1. A method of forming a semiconductor device, comprising the steps of:

providing a first semiconductor region of a first conductivity type;

providing a patterned oxide layer over the first semiconductor region;

forming a second semiconductor region of a second conductivity type in the first semiconductor region and aligned to an opening in the patterned oxide layer;

forming a first insulating layer aligned to the opening in the patterned oxide layer;

centering a trench within the second semiconductor region, wherein the trench extends from a surface of the second semiconductor region through the first and second semiconductor regions and the trench is aligned to the first insulating layer;

filling the trench with a conductive material;

covering the conductive material with a second insulating layer;

removing the oxide layer to expose an edge of the first insulating layer; and

aligning an implant layer to the edge of the first insulating layer, where the implant layer is disposed in the first semiconductor region adjacent to the second semiconductor region.

2. The method of claim 1, wherein forming a first insulating layer includes forming a spacer.

3. The method of claim 1, wherein the implant layer further comprises enhancing the conductivity of a portion of the first semiconductor region adjacent the second semiconductor region.

4. A method of forming a power switching transistor, comprising the steps of:

providing a substrate;

forming a first conduction region in the substrate;

forming a second conduction region within the first conduction region;

forming a trench from a surface of the second conduction region and extending through the first and second conduction regions;

forming a control region in the trench; and

forming a multi-layered insulating material having a first layer that covers a portion of the second semiconductor region but not covering a portion of the trench and a second layer covering the portion of the trench not covered by the first layer.

5. The method of claim 4, further including the step of using the multi-layered insulating material to mask the second conduction region in forming a third conduction region adjacent to the second conduction region.

6. The method of claim 5, further including the step of connecting the second conduction region and third conduction region with a metal.

7. A method of forming a power switching transistor, comprising the steps of:

providing a first semiconductor region of a first conductivity type;

forming a plurality of source regions in the first semiconductor region, where each source region is separated from an adjacent source region by a band of the first semiconductor region;

providing a patterned first insulating layer over the source regions and bands of the first semiconductor region;

forming spacers along an edge of the patterned first insulating layer;

aligning a trench to the spacers and intersecting a portion of the plurality of source regions, where the trench extends through the plurality of source regions;

filling the trench with a conductive material;

covering the conductive material with a second insulating layer; and

implanting the band of the first semiconductor region with a first conductivity type.