System and method for maintaining memory coherency in a computer system having multiple system buses

• US 5,897,656 A
• Filed: 09/16/1996
• Issued: 04/27/1999
• Est. Priority Date: 09/16/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Corollary, Inc. (Intel Corporation)
• Inventors: Vogt, Pete D., White, George P., Chang, Stephen S.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Portka, Gary J.
• Application Number:
  US08/714,750
• Time in Patent Office: 953 Days
• Field of Search: 711/141, 711/144, 711/148, 711/149, 395/308
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)

Abstract

A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.

Claims

1. A multiple-bus, multiprocessing system comprising:

a system memory;

a first bus in communication with said system memory, said first bus having at least one cache memory coupled thereto, said cache memory configured to store a plurality of data values obtained from said system memory, said cache memory further configured to maintain cache coherency information about said data values with a first set of coherency states;

a coherency memory in communication with said first bus, said coherency memory configured to maintain a coherency status record associated with said data values;

a second bus in communication with said system memory, said second bus capable of transmitting a bus transaction; and

a coherency filter in communication with said second bus and said coherency status record, but not connected to said first bus, said coherency filter configured to monitor said bus transaction on said second bus and to inhibit cross-bus transactions from said second bus to said first bus based on said coherency status record.

2. The system of claim 1 further comprising a first plurality of cache memories coupled to said first bus, wherein said cache memories maintain cache coherency information with said first set of coherency states.

3. The system of claim 1 wherein said bus transaction identifies a memory address associated with one of said data values.

4. The system of claim 3 wherein said coherency status record contains a plurality of entries wherein each of said entries is configured to store a memory address associated with a data value stored in said cache memory.

5. The system of claim 4 wherein each of said entries is configured to store a second set of coherency states which comprise fewer coherency states than said first set of coherency states.

6. The system of claim 5 wherein each of said entries is further configured to store at least one of said second set of coherency states.

7. The system of claim 6 wherein each of said memory addresses is directly mapped to one of said entries.

8. A method of maintaining cache coherency in a multiple-bus system comprising:

maintaining cache status information associated with a first plurality of data values existing in a cache unit coupled to a first bus;

maintaining a first-bus coherency status record associated with said first plurality of data values;

monitoring with a first coherency filter bus transactions on said first bus;

monitoring with a second coherency filter, bus transactions on a second bus;

transmitting a bus transaction on said second bus; and

inhibiting with said second coherency filter a cross-bus transaction from said second bus to said first bus when said first-bus coherency status record indicates that memory incoherency will not result from inhibiting said cross-bus transaction.

9. The method of claim 8 wherein said first-bus coherency status record maintains at least one entry for each of said data values.

10. The method of claim 9 wherein said act of inhibiting further comprises the act of consulting said entry in said first-bus coherency status record associated with said bus transaction to determine whether said entry is an invalid state.

11. The method of claim 9 wherein said act of inhibiting further comprises the act of consulting said entry in said first-bus coherency status record associated with said bus transaction to determine whether said entry is a shared state.

12. The method of claim 11 further comprising the act of modifying said entry associated with said bus transaction when said entry is in an owned state.

13. The method of claim 11 further comprising the act of modifying said entry associated with said bus transaction from an owned state to a shared state.

14. The method of claim 11 further comprising the act of modifying said entry associated with said bus transaction from an owned state to an invalid state.

15. A multiple-bus, multiprocessing system comprising:

a system memory;

a system bus in communication with said system memory, said system bus having at least one cache memory coupled thereto, said cache memory configured to store a plurality of data values obtained from said system memory, said first system bus capable of transmitting multiple bus transactions;

a coherency memory in communication with said system bus, said coherency memory configured to maintain a system bus coherency status record associated with said data values;

an Input/Output bus in communication with said system memory, said Input/Output bus capable of transmitting multiple bus transactions;

an Input/Output coherency filter in communication with said Input/Output bus and said coherency memory said Input/Output coherency filter configured to monitor said bus transactions on said Input/Output bus but not bus transactions on said system bus, said Input/Out put coherency filter further configured to inhibit cross-bus transactions from said Input/Out put bus to said system bus based on said system bus coherency status record.

16. The system of claim 15 wherein said Input/Output coherency filter is further configured to monitor direct memory accesses on said I/O bus and to perform cross-bus transactions which are necessary to avoid the flushing of cache lines in said cache memory.

17. The system of claim 15 wherein said Input/Output bus further comprises a plurality of I/O bridges which contain internal I/O cache memories, said I/O cache memories configured to store a second plurality of data values, said I/O cache memories further configured to maintain cache coherency information about said second plurality of data values.

18. The system of claim 17 further comprising an I/O coherency memory in communication with said I/O bus, said I/O coherency memory configured to maintain an I/O coherency status record associated with said second plurality of data values.

19. The system of claim 18 further comprising a system bus coherency filter in communication with said system bus and said I/O coherency memory, said system bus coherency filter configured to monitor said bus transaction on said system bus and to inhibit cross-bus transactions from said system bus to said I/O bus based on said I/O coherency status record.

20. A method of maintaining cache coherency in a multiple-bus system comprising:

maintaining cache status information associated with a first plurality of data values existing in a cache unit coupled to a system bus, said cache status information based on a first set of coherency states;

maintaining a coherency status record associated with said first plurality of data values;

monitoring with a first coherency filter bus transactions on said system bus;

monitoring with a second coherency filter bus transactions on an Input/Out put bus;

transmitting a bus transaction on said Input/Output bus; and

inhibiting with said second coherency filter a cross-bus transaction from said Input/Out put bus to said system bus when said coherency status record indicates that memory incoherency will not result from inhibiting said cross-bus transaction.

21. The method of claim 20 wherein said act of transmitting a bus transaction on an Input/Output bus is a direct memory access.

22. The system of claim 20 further comprising the act of caching a plurality of I/O data values transferred on said I/O bus.

23. The system of claim 22 further comprising the act of maintaining cache status information associated with said I/O data values.

24. The method of claim 23 further comprising the act of maintaining an I/O coherency status record associated with said I/O data values.

25. The method of claim 24 further comprising the acts of:

transmitting a bus transaction on said system bus; and

inhibiting with said second coherency filter a cross-bus transaction from said system bus to said I/O bus when said I/O coherency status record indicates that memory incoherency will not result from inhibiting said cross-bus transaction from said system bus to said I/O bus.

26. A multiple-bus, multiprocessing system comprising:

a system memory;

a first system bus and a second system bus in communication with said system memory, said first system bus having at least one cache memory coupled thereto, and said second system bus having at least one cache memory coupled thereto, said cache memories configured to store a plurality of data values obtained from said system memory;

a first coherency memory in communication with said first system bus, said first coherency memory configured to maintain a first coherency status record associated with said data values in said cache units connected to said first system bus;

a second coherency memory in communication with said second system bus, said second coherency memory configured to maintain a second coherency status record associated with said data values in said cache memories connected to said second system bus;

a first coherency filter in communication with said first system bus and said second coherency memory, said first coherency filter configured to monitor bus transactions on said first system bus and to inhibit cross-bus transactions from said first system bus to said second system bus based on said second coherency status record; and

a second coherency filter in communication with said second system bus and said first coherency memory, said second coherency filter configured to monitor bus transactions on said second system bus and to inhibit cross-bus transactions from said second system bus to said first system bus based on said first coherency status record.

27. The system of claim 26 further comprising:

an I/O bus in communication with said system memory and a plurality of I/O devices which store I/O data values in at least one I/O cache memory; and

an I/O coherency memory in commnunication with an I/O bus, said I/O coherency memory configured to maintain an I/O coherency status record associated with said I/O data values.

28. The system of claim 27 wherein said first coherency filter is also in communication with said I/O coherency memory, and wherein said first coherency filter is configured to monitor bus transactions on said first system bus and to inhibit cross-bus transactions from said first system bus to said I/O bus based on said I/O coherency status record.

29. The system of claim 27 further wherein said a second coherency filter is also in communication with said I/O coherency memory, and wherein said second coherency filter is configured to monitor bus transactions on said second system bus and to inhibit cross-bus transactions from said second system bus to said I/O bus based on said I/O coherency status record.

30. The system of claim 27 further comprising an I/O coherency filter in communication with said first coherency memory and said second coherency memory, said I/O coherency filter configured to monitor bus transactions on said I/O bus and to inhibit cross-bus transactions from said I/O bus to said first system bus based on said first coherency status record and to inhibit cross-bus transactions from said I/O bus to said second system bus based on said second coherency status record.

31. A multiple-bus, multiprocessing system comprising:

a system memory;

a first bus and a second bus in communication with said system memory, said first bus having at least one cache memory coupled thereto and said second bus having at least one cache memory coupled thereto, said cache memories configured to store a plurality of data values obtained from said system memory, said cache memories further configured to maintain cache coherency information about said data values;

a first coherency memory means for maintaining a first coherency status record of said data values associated with said first bus;

a second coherency memory means for maintaining a second coherency status record of said data values associated with said second bus;

a first coherency filter means for monitoring bus transactions on said first bus and for inhibiting cross-bus transactions from said first bus to said second bus based on said second coherency status record; and

a second coherency filter means for monitoring bus transactions on said second bus and for inhibiting cross-bus transactions from said first bus to said second bus based on said first coherency status record.

32. A multiple-bus, multiprocessing system comprising:

a system memory;

a first bus in communication with said system memory, said first bus having at least one cache memory coupled thereto, said cache memory configured to store a plurality of data values obtained from said system memory, said cache memory further configured to maintain coherency status information about said data values;

a coherency memory in communication with said first bus, said coherency memory configured to maintain a coherency status record associated with said data values with a second set of coherency states wherein said second set of coherency states are different than said first set of coherency states;

a second bus in communication with said system memory, said second bus capable of transmitting a bus transaction; and

a coherency filter in communication with said second bus and said coherency memory, said coherency filter configured to monitor bus transactions on said second bus, but not monitor bus transactions on said first bus, said coherency filter configured to inhibit cross-bus transactions from said second bus to said first bus based on said coherency status record.

33. The system of claim 32 wherein said coherency filter further comprises a first coherency memory controller which is configured to receive a bus transaction address, said first coherency memory controller further configured to access an entry in said coherency status record which corresponds to said bus transaction address.

34. The system of claim 33 wherein said first coherency memory controller obtains said coherency state existing in said entry.

35. The system of claim 34 wherein said coherency filter further comprises a cycle encoder which identifies a bus transaction code which identifies said bus transaction.

36. The system of claim 35 wherein said coherency filter further comprises a rules table which receives said coherency status and a bus transaction code which identifies said bus transaction.

37. A method of maintaining cache coherency in a multiple-bus system comprising:

maintaining cache status information associated with a first plurality of data values existing in a cache unit coupled to a first bus, said cache status information based on a first set of coherency states;

maintaining a coherency status record associated with said data values, said coherency status record based on a second set of coherency states wherein said second set of coherency states are different that said first set of coherency states;

monitoring with a first coherency filter bus transactions on said first bus;

monitoring with a second coherency filter bus transactions on a second bus;

transmitting a bus transaction on said second bus; and

inhibiting with said second coherency filter a cross-bus transaction from said second bus to said first bus when said coherency status record indicates that memory incoherency will not result from inhibiting said cross-bus transaction.

38. The method of claim 37 further comprising the act of accessing an entry in said coherency status record which corresponds to a bus transaction address.

39. The method of claim 38 further comprising the act of obtaining said coherency state existing in said entry.

40. The method of claim 39 further comprising the act of encoding said bus transaction code to generate a bus transaction code which identifies said bus transaction.

41. The method of claim 40 further comprising the act of evaluating said bus transaction code and said coherency state to determine whether a cross-bus transaction is necessary to maintain cache coherency.

42. A multiple-bus, multiprocessing system comprising:

a system memory;

a first bus and a second bus in communication with said system memory, said first bus having a plurality of cache memories coupled thereto and said second bus having a plurality of cache memories coupled thereto, said cache memories configured to perform snoop operations and maintain cache status information for a plurality of data values obtained from said system memory, said cache memories further configured to internally modify said cache status information associated with some of said data values without outputting said internal modifications;

a coherency memory in communication with said first bus, said coherency memory configured to maintain a coherency status record associated with said data values obtained by a cache memory on said first bus; and

a coherency filter in communication with said second bus and said coherency memory, said coherency filter configured to monitor bus transactions on said second bus and not configured to monitor transactions on said first bus, said coherency filter further configured to inhibit cross-bus transactions from said second bus to said first bus based on said coherency status record.

43. A method of maintaining cache coherency in a multiple-bus system comprising:

maintaining cache status information associated with a first plurality of data values existing in a cache unit coupled to a first system bus;

internally modifying said cache status information in said cache unit without outputting said internal modification;

maintaining a coherency status record associated with said data values;

monitoring with a coherency filter, bus transactions on a second bus but not bus transactions on said first bus;

transmitting a bus transaction on said second bus; and

inhibiting a cross-bus transaction from said second system bus to said system bus when said coherency status record indicates that memory incoherency will not result from inhibiting said cross-bus transaction.