Reduced terminal testing system

• US 5,898,186 A
• Filed: 09/13/1996
• Issued: 04/27/1999
• Est. Priority Date: 09/13/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beffa, Raymond J., Farnworth, Warren M., Cloud, Eugene H., Nevill, Leland R.
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/713,606
• Time in Patent Office: 956 Days
• Field of Search: 257/48, 257/202, 257/203, 257/207, 257/208, 257/209, 257/529, 257/530, 324/765
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2841 Signal generators
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2868 Complete testing stations; systems; procedures; software aspects
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.

Claims

1. A semiconductor wafer comprising:

a substrate;

a plurality of dice located on the substrate, the plurality of dice including circuitry for placing an individual die of the plurality of dice into a mode upon receipt of an alternating signal having a predetermined characteristic by the circuitry; and

a conductive path connected to the circuitry providing the alternating signal to the circuitry.

2. The wafer of claim 1, wherein the conductive path substantially simultaneously carries a VCC power signal to the circuitry.

3. The wafer of claim 2, wherein the alternating signal is substantially superimposed on the VCC power signal.

4. The wafer of claim 1, wherein the predetermined characteristic is a first characteristic, and whereby the circuitry is placed in a different mode in response to the alternating signal having a second characteristic.

5. The wafer of claim 1, wherein the plurality of dice is a first plurality of dice, the circuitry is a first set of circuitry, the mode is a first mode, the conductive path is a first path, the alternating signal is a first alternating signal, and the predetermined characteristic is a first characteristic, and wherein the wafer further comprises:

a second plurality of dice on the substrate, the second plurality of dice including a second set of circuitry placing the second plurality of dice into a second mode when the second set of circuitry receives a second alternating signal having a second predetermined characteristic; and

a second conductive path providing the second alternating signal to the second set of circuitry of the second plurality of dice.

6. The wafer of claim 5, wherein a predetermined reference signal is applied to the first plurality of dice.

7. The wafer of claim 1, wherein the plurality of dice is a first plurality of dice, the mode is a first mode, the alternating signal is a first alternating signal, and the predetermined characteristic is a first predetermined characteristic, and wherein the wafer further comprises a second plurality of dice, such second plurality of dice not being placed into the first mode in response to an alternating signal have the first predetermined characteristic.

8. The wafer of claim 1, wherein the circuitry includes first and second sections, and the first section receives the alternating signal including placing the second section into the mode.

9. The wafer of claim 1, wherein the mode includes a stressing mode for stressing the dice.

10. The wafer of claim 1, wherein the mode includes a repair mode.

11. The wafer of claim 1, wherein the alternating signal and a VCC power signal are received through a single contact on each die of the plurality of dice.

12. The wafer of claim 1, wherein the alternating signal includes a clock signal, the circuitry determining clock information therefrom.

13. The wafer of claim 1, wherein the plurality of dice include additional circuitry producing a signal indicating the occurrence of a predetermined event.

14. The wafer of claim 12, further comprising:

a fuse, the fuse being blown at the completion of the mode.

15. The wafer of claim 12, further comprising:

an anti-fuse, the anti-fuse being blown at the completion of the mode.

16. The wafer of claim 12, further comprising:

a flash device, the flash device being blown at the completion of the mode.

17. The wafer of claim 1, further comprising:

a plurality of street areas formed between adjacent individual die of the plurality of dice, the conductive path being formed in predetermined street areas of the plurality of street areas between predetermined individual die of the plurality of dice.

18. The wafer of claim 1, further comprising:

a plurality of buffers connected to the conductive path, a predetermined individual buffer of the plurality of buffers preventing a predetermined individual die of the plurality of dice from receiving the alternating signal until such predetermined individual buffer associated with said predetermined individual die is enabled.

19. An electronic device, comprising:

processing circuitry and memory circuitry, at least one of the processing and memory circuitry including;

a substrate; and

a die located on the substrate, the die including circuitry for placing the die into a mode upon receipt of an alternating signal having a predetermined characteristic by the circuitry.

20. The device of claim 19, wherein the die includes a conductive path that substantially simultaneously carries a VCC power signal to the circuitry.

21. The device of claim 19, wherein the predetermined characteristic is a first characteristic, and whereby the circuitry is placed in a different mode in response to the alternating signal having a second characteristic.

22. The device of claim 19, wherein the device is a computer system.

23. The device of claim 19, wherein the device is a printer.

24. A semiconductor wafer comprising:

a substrate;

a plurality of dice located on the substrate, the plurality of dice each responding to a particular identification code and each including circuitry for placing individual die of the plurality of dice into a mode upon receipt of an alternating signal having the particular identification code; and

a conductive path connected to the circuitry providing the alternating signal to the circuitry.

25. A semiconductor wafer comprising:

a substrate;

a conductive path associated with the substrate for carrying an alternating signal and another signal at the same time; and

a plurality of dice fabricated on the substrate, with at least one of the dice including;

an external terminal coupled to the conductive path for receiving the alternating signal and the other signal at the same time; and

internal circuitry coupled to the external terminal for outputting an internal die signal substantially responsive to the alternating signal and at most insubstantially responsive to the other signal.

26. The semiconductor wafer of claim 25, further comprising a probe pad positioned on the substrate and coupled to the conductive path.

27. The semiconductor wafer of claim 25 wherein the conductive path comprises a conductive trace for carrying an alternating signal selected from a group comprising a digital signal and an analog signal and for carrying another signal selected from a group comprising a digital signal, an analog signal, and a supply voltage signal.

28. The semiconductor wafer of claim 27 wherein the conductive trace comprises a conductive trace for carrying an alternating signal selected from a group comprising an amplitude-modulated signal, a frequency-modulated signal, a pulse-width-modulated signal, and a phase-shift-keying-modulated signal.

29. The semiconductor wafer of claim 25 wherein the conductive path comprises a conductive trace for carrying an alternating signal comprising one-half of a differential alternating signal, wherein the semiconductor wafer further comprises an additional conductive path associated with the substrate for carrying the other half of the differential alternating signal, wherein the internal circuitry comprises differential circuitry, wherein the at least one die further comprises an additional external terminal coupled to the additional conductive path and the internal circuitry for receiving the other half of the differential alternating signal and conducting said signal to the internal circuitry.

30. The semiconductor wafer of claim 25 wherein the external terminal comprises a bond pad.

31. The semiconductor wafer of claim 25 wherein the internal circuitry includes at least one of filtering circuitry, clock extraction circuitry, buffering circuitry, differential circuitry, and demodulation circuitry.

32. The semiconductor wafer of claim 25 wherein the internal circuitry comprises circuitry for outputting at least one of an internal data signal, an internal control signal, and an internal clock signal.

33. The semiconductor wafer of claim 25 wherein the at least one die further comprises additional internal circuitry coupled to the external terminal for outputting another internal die signal substantially responsive to the other signal and at most insubstantially responsive to the alternating signal.

34. The semiconductor wafer of claim 33 wherein the additional internal circuitry comprises at least one of voltage regulation circuitry and input buffer circuitry.

35. The semiconductor wafer of claim 25 wherein the internal circuitry comprises an input buffer, wherein the at least one die further comprises an additional external terminal coupled to the input buffer for conducting an externally generated reference signal thereto.

36. The semiconductor wafer of claim 25 wherein the internal circuitry comprises demodulation circuitry, wherein the at least one die further comprises an additional external terminal coupled to the demodulation circuitry for conducting a reference local oscillator signal thereto.