Semiconductor package bond post configuration

• US 5,898,213 A
• Filed: 07/07/1997
• Issued: 04/27/1999
• Est. Priority Date: 07/07/1997
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sharma, Laxminarayan, Torres, Victor Manuel, Srikantappa, Ashok
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/888,392
• Time in Patent Office: 659 Days
• Field of Search: 257/666, 257/786, 257/667, 257/672, 257/676, 257/737, 257/738, 257/778
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A bond post configuration for wire bonded semiconductors has bond posts grouped in three posts where two are arranged closely to a side of a die about a first axis and a third is arranged in between and further removed from the side about a second axis. In one form, the bond post configuration is a radial configuration. Additionally, conductive traces which extend from the bond posts and away from the die are placed off-center from the the bond posts about the first axis to provide more placement area for the bond posts arranged about the second axis. The bond post configuration may be utilized in any wire bonded semiconductor.

Claims

1. A semiconductor package comprising:

a die having a plurality of bond pads;

a package layer having a plurality of conductive paths, each of the plurality of conductive paths having a conductive bond post at one end, wherein a first portion of the plurality of conductive bond posts is arranged along a first axis and a second portion of the plurality of conductive bond posts is arranged along a second axis, the first and second portions having different number of bond posts, each of the plurality of conductive bond posts having a center axis;

a plurality of wire bonds electrically connecting the plurality of bond pads to the plurality of conductive bond posts;

wherein conductive paths are selectively off-set from the center axis of the first portion of conductive bond posts.

2. A package as in claim 1, further wherein the first portion of conductive bond posts includes approximately 66 per cent of the plurality of conductive bond posts.

3. A package as in claim 1, wherein the first axis is between the die and the second axis.

4. A package as in claim 1, wherein the first and second axis are parallel to sides of the die.

5. A package as in claim 1, wherein the first and second axes are positioned radially around the die.

6. A package as in claim 5, wherein the die has a focal point, and the first portion of bond posts is within a 45°

angle projection centered at the focal point with the center axis of each conductive bond post coincident with the focal point.

7. A package as in claim 5, wherein at least one of the plurality of conductive paths is directed towards the die.

8. A package as in claim 1, wherein the package is a ball pad grid array package.

9. A package as in claim 1, wherein the package has a leadframe.

10. A package as in claim 1, wherein a first gap between immediately adjacent conductive paths of two of the first portion of bond posts is substantially less than a second gap between immediately adjacent conductive paths of one of the first portion of bond posts and one of the second portion of bond posts.

11. A package as in claim 1, wherein the package is encapsulated with a molding component.

12. A package as in claim 1, wherein the package is encapsulated with a glob top.

13. A package as in claim 1, wherein the package is a wire bonded package.

14. A package as in claim 13, wherein the package is one of a plastic ball grid array, a ceramic ball grid array, a quad flat pack, a small outline "J" lead, a small outline integrated circuit, a thin small outline package, a dual in line package, a pin grid array, a plastic leaded chip carrier, or a tape automated bonding.

15. A ball grid array semiconductor device comprising:

a package substrate having a first plurality of conductive traces formed thereon and has a conductive bond post at an end of each trace, the package substrate having a plurality of conductive terminal pads arranged in an array configuration and electrically connected to the plurality of conductive traces, wherein the conductive bond posts are arranged along a first and a second axis, wherein the first axis contains a majority of the conductive bond posts;

a semiconductor die mounted to the package substrate, the die having a periphery and sides, and having a plurality of bond pads located about the periphery of the die, wherein the first and second axis on the package substrate are radially placed outside the periphery of the die; and

a first plurality of wire bonds electrically connecting the plurality of bond pads of the semiconductor die to the conductive bond posts on the package substrate.

16. A device as in claim 15, wherein the first and second axes are proportionately placed within octants around the periphery of the die, the octants defined by angular projections from at least one focal point on the semiconductor die.

17. A device as in claim 15, wherein the first and second axis form an arc shape.

18. A device as in claim 15, wherein the conductive traces are directed from the conductive bond posts toward the semiconductor die.

19. A device as in claim 15, wherein the package substrate is an epoxy-glass based substrate.

20. A semiconductor package, comprising:

a die having a plurality of bond pads;

a staggered wirebonding configuration, the wirebonding configuration electrically coupled to the plurality of bond pads, the configuration comprising;

a first bond post having a conductive trace, the first bond post positioned on a first axis; and

second and third bond posts positioned on a second axis, the second axis being a constant distance from the first axis, the second and third bond posts positioned on each side of the first bond post.

21. A semiconductor package as in claim 20, wherein the first axis is closer to the die than the second axis.