Chip-on-chip IC packages
First Claim
Patent Images
1. Integrated circuit package comprising:
- a. a first integrated circuit chip containing a plurality of active semiconductor devices, said first integrated circuit chip having a length L1, a width W1, an upper planar surface with area A1 equal to L1 ×
W1, and a lower planar surface with area A1,b. a first interconnection circuit on said upper planar surface of said first integrated circuit chip,c. a second integrated chip supported by said first chip, said second integrated circuit chip containing a plurality of active semiconductor devices and having a length L2, a width W2, an upper planar surface with area A2 equal to L2 ×
W2, and a lower planar surface with area A2, and where A2 <
A1,d. a plurality of bonding means for bonding said lower planar surface of said second integrated circuit chip to said upper planar surface of said first integrated circuit chip, leaving a space between said lower planar surface of said second integrated circuit chip and said upper planar surface of said first integrated circuit chip, ande. a second interconnection circuit on the lower planar surface of said second integrated circuit chip, andf. a plurality of runners in each of said first and second interconnection circuits and in which at least some of the runners in said first interconnection circuit electrically connect two of said plurality of bonding means and at least some of the runners in said second interconnection circuit electrically connect two of said plurality of bonding means.
12 Assignments
0 Petitions
Accused Products
Abstract
The specification describes interconnection layouts for chip-on-chip packages using solder bump interchip connections as vias between a single level metal interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper IC chip. This arrangement allows for the formation of air isolated crossovers of features on either chip.
145 Citations
15 Claims
-
1. Integrated circuit package comprising:
-
a. a first integrated circuit chip containing a plurality of active semiconductor devices, said first integrated circuit chip having a length L1, a width W1, an upper planar surface with area A1 equal to L1 ×
W1, and a lower planar surface with area A1,b. a first interconnection circuit on said upper planar surface of said first integrated circuit chip, c. a second integrated chip supported by said first chip, said second integrated circuit chip containing a plurality of active semiconductor devices and having a length L2, a width W2, an upper planar surface with area A2 equal to L2 ×
W2, and a lower planar surface with area A2, and where A2 <
A1,d. a plurality of bonding means for bonding said lower planar surface of said second integrated circuit chip to said upper planar surface of said first integrated circuit chip, leaving a space between said lower planar surface of said second integrated circuit chip and said upper planar surface of said first integrated circuit chip, and e. a second interconnection circuit on the lower planar surface of said second integrated circuit chip, and f. a plurality of runners in each of said first and second interconnection circuits and in which at least some of the runners in said first interconnection circuit electrically connect two of said plurality of bonding means and at least some of the runners in said second interconnection circuit electrically connect two of said plurality of bonding means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. Integrated circuit package comprising:
-
a. a first integrated circuit chip, said first integrated circuit chip containing a plurality of active semiconductor devices and having a length L1, a width W1, an upper planar surface with area A1 equal to L1 ×
W1, and a lower planar surface with area A1,b. a first interconnection circuit on said upper planar surface of said first integrated circuit chip, c. a second integrated chip supported by said first chip, said second integrated circuit chip containing a plurality of active semiconductor devices and having a length L2, a width W2, an upper planar surface with area A2 equal to L2 ×
W2, and a lower planar surface with area A2, and where A2 <
A1,d. a third integrated chip supported by said first chip, said third integrated circuit chip containing a plurality of active semiconductor devices having a length L3, a width W3, an upper planar surface with area A3 equal to L3 ×
W3, and a lower planar surface with area A3, and where A3 <
A1, and further where A2 +A3 <
A1, L2 +L3 <
L1, and W2 and W3 <
W1,e. a plurality of bonding means for bonding said lower planar surfaces of said second and third integrated circuit chips to said upper planar surface of said first integrated circuit chip, leaving space between said lower planar surfaces of said second and third integrated circuit chips and said upper planar surface of said first integrated circuit chip, f. a second interconnection circuit on the lower planar surface of said second integrated circuit chip, and g. a third interconnection circuit on the lower planar surface of said third integrated circuit chip, and h. a plurality of runners in each of said first, second, and third interconnection circuits and in which at least some of the runners in said first, second and third interconnection circuit electrically connect two of said plurality of bonding means. - View Dependent Claims (12, 13, 14, 15)
-
Specification