Method and apparatus for slew rate and impedance compensating buffer circuits

• US 5,898,321 A
• Filed: 03/24/1997
• Issued: 04/27/1999
• Est. Priority Date: 03/24/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kleveland, Bendik, Ilkbahar, Alper
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/824,066
• Time in Patent Office: 764 Days
• Field of Search: 326/24, 326/27, 326/83, 326/86, 326/87, 326/121, 326/30, 327/170
• US Class Current: 326/87
• CPC Class Codes: H03K 17/164 using parallel switching arrangements

Abstract

A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit, which includes a slew rate compensation circuit, coupled to a driver circuit, which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground to provide a variable resistance to virtual rails for inverter circuits that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals. The impedance compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground from an output node of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals. The resistance to power and ground from the respective rails of the pre-driver circuit are controlled with the slew rate control signals to adjust the slew rate of data signals being driven by the buffer. The rails are shared among the inverters of the driver circuit to reduce the number of devices used by the buffer, thereby reducing the amount of circuit area and power used by the buffer.

Claims

1. A compensated buffer circuit, comprising:

a pre-driver circuit including a slew rate compensation circuit, the pre-driver circuit coupled to receive a data signal, the slew rate compensation circuit coupled to receive a slew rate control signal to control a first variable resistance of the slew rate compensation circuit to a first potential and a second variable resistance of the slew rate compensation circuit to a second potential; and

a driver circuit including impedance compensation circuit, the driver circuit coupled to the pre-driver circuit to receive an output of the pre-driver circuit, the impedance compensation circuit coupled to receive an impedance control signal, the driver circuit coupled to output an output of the impedance control circuit at an output node.

2. The compensated buffer circuit described in claim 1 wherein an output impedance of the compensated buffer circuit varies in response to the impedance control signal.

3. The compensated buffer circuit described in claim 1 wherein a slew rate of the output of the pre-driver circuit varies in response to the slew rate control signal.

4. The compensated buffer circuit described in claim 1 further comprising a compensation unit, the compensation unit coupled to generate the slew rate control signal and the impedance control signal.

5. The compensated buffer circuit described in claim 1 wherein the impedance compensation circuit comprises:

a first plurality of transistors coupled in parallel between the output node and the first potential, the first plurality of transistors varying the output impedance of the compensated buffer circuit between the output node and the first potential in response to the impedance control signal; and

a second plurality of transistors coupled in parallel between the output node and the second potential, the second plurality of transistors varying the output impedance of the compensated buffer circuit between the output node and the second potential in response to the output of the pre-driver circuit.

6. The compensated buffer circuit described in claim 5 wherein the pre-driver circuit comprises a first plurality of inverter circuits coupled between first and second rails, each one of the first plurality of inverter circuits coupled to receive the data signal, each one of the first plurality of inverter circuits generating an output coupled to a gate of a corresponding one of the second plurality of transistors.

7. The compensated buffer circuit described in claim 6 wherein the slew rate compensation circuit comprises:

a third plurality of transistors coupled in parallel between the first rail and the first potential; and

a fourth plurality of transistors coupled in parallel between the second rail and the second potential;

wherein the third and fourth plurality of transistors are coupled to the slew rate control signal such that third and fourth plurality of transistors vary the slew rate of the output of the pre-driver circuit in response to the slew rate control signal.

8. The compensated buffer circuit described in claim 1 wherein the slew rate and impedance control signals are generated by a compensation unit.

9. The compensated buffer circuit described in claim 1 wherein the compensated buffer circuit is further coupled to receive an output enable signal, the driver circuit outputting the output of the impedance control circuit in response to the output enable signal.

10. The compensated buffer circuit described in claim 1 wherein the compensated buffer circuit is a compensated input/output buffer.

11. A method for buffering a data signal generated at an input/output node of an integrated circuit, the method comprising the steps of:

receiving the data signal with a pre-driver circuit;

varying a first variable resistance of the pre-driver circuit to a first potential and a second variable resistance of the pre-driver circuit to a second potential to vary a resistor-capacitor (RC) time constant between the pre-driver circuit and a driver circuit coupled to an output of the pre-driver circuit to control a slew rate in an output of the pre-driver circuit;

receiving the output of the pre-driver circuit with the driver circuit, the driver circuit to output an output of the driver circuit;

varying an output impedance of the driver circuit such that the output impedance of the driver circuit matches a line impedance of a line coupled to the output node.

12. The method described in claim 11 including the additional step of generating a slew rate control signal wherein the step of varying the RC time constant is performed in response to the slew rate control signal.

13. The method described in claim 11 including the additional step of generating an impedance control signal wherein the step of varying the output impedance is performed in response to the impedance control signal.

14. An input/output buffer circuit, comprising:

pre-driver means for receiving a data signal and transmitting an output of the pre-driver means;

slew rate compensation means included in the pre-driver means for controlling a slew rate of the output of the pre-driver means in response to a slew rate compensation signal controlling a first variable resistance to a first potential and a second variable resistance to a second potential of the slew rate compensation means;

driver means coupled to the pre-driver means for receiving the output of the pre-driver means and transmitting an output of the driver means; and

impedance compensation means included in the driver means for controlling an output impedance of the input/output buffer circuit in response to an impedance control signal.

15. The input/output buffer circuit described in claim 14 further comprising:

means for generating the slew rate compensation signal coupled to the slew rate compensation means; and

means for generating the impedance control signal coupled to the impedance compensation means.