Semiconductor nonvolatile memory and source circuit for this memory

• US 5,898,616 A
• Filed: 11/14/1997
• Issued: 04/27/1999
• Est. Priority Date: 05/08/1997
• Status: Expired due to Fees

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Ono, Takashi
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US08/970,500
• Time in Patent Office: 529 Days
• Field of Search: 365/185.17, 365/185.11, 365/185.13, 365/230.03, 365/63
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

In order to prevent sub bit line disturbance without leading to an increase in the current required for the write inducing new disturbance-related problems, the semiconductor nonvolatile memory according to the present invention comprises sub bit lines mutually connected in parallel with the drain(s) of the memory cells connected with a plurality of word lines for grouping the memory cells in units of a plurality of word lines, sub bit line selection transistors that connects the sub bit line to the bit line in a manner such that connection thereof can be interrupted, a sub source line connected to the source of the memory cells in a block grouped by the bit lines, and a block selection transistor that connects the sub source line to the source line interruptably. Prior to a write of data into at least an individual memory cell, the sub bit line selection transistors and the block selection transistor involved with one group interlock with each other in order to connect only the sub bit lines and the sub source line corresponding to the selected group to the bit lines and the source line respectively.

Claims

1. A NOR type semiconductor nonvolatile memory in which a data overwrite employing an FN tunnel current is possible, comprising:

a plurality of memory cells each having a control gate and a floating gate connected to a word line, a source connected to a source line and a drain connected to a bit line;

sub bit lines mutually connected in parallel with said drains of said memory cells connected with a plurality of word lines for grouping said memory cells in units of a plurality of word lines;

sub bit line selection transistors that connect said sub bit lines to said bit line interruptably;

a sub source line connected to said source of said memory cells in a block grouped by said bit lines; and

a block selection transistor that connects said sub source line to said source line interruptably, wherein;

prior to a write of data into one or more memory cells, said sub bit line selection transistors and said block selection transistor corresponding to a group interlock with each other in order to connect only said sub bit lines and said sub source line corresponding to a selected group to said bit line and said source line respectively.

2. A NOR type semiconductor nonvolatile memory according to claim 1, wherein:

during write of data into said memory cells, said sub bit line selection transistors and said block selection transistor corresponding to a selected block are set in a state of electrical continuity, with a voltage corresponding to said data applied to said sub bit lines within said selected block, a negative voltage applied to said word line that has been selected within said block, a positive voltage applied to said word lines that have not been selected within said block, and said sub bit line selection transistors and said block selection transistor corresponding to remaining unselected blocks are set in a cutoff state.

3. A NOR type semiconductor nonvolatile memory according to claim 1, wherein:

during a delete of data from said memory cells, said sub bit line selection transistor and said block selection transistor corresponding to a selected block are set in a state of electrical continuity, with a negative voltage applied to said sub bit lines within said selected block, a positive voltage applied to said word line that has been selected within said block and a negative voltage applied to said word lines that have not been selected within said block.

4. A NOR type semiconductor nonvolatile memory, comprising:

a plurality of memory cells each having a control gate and a floating gate connected to a word line, a source connected to a source line and a drain connected to a bit line incorporated in a semiconductor substrate;

a bipolar voltage circuit mounted in said semiconductor substrate in order to perform overwrite of data by employing an FN tunnel current, with which overwrite is possible;

sub bit line selection transistors that connect said sub bit lines to said bit line interruptably;

a sub source line connected to said source of said memory cells in a block grouped by said bit lines; and

a block selection transistor that connects said sub source line to said source line interruptably, wherein;

prior to a write of data into one or more memory cells, said sub bit line selection transistors and said block selection transistor corresponding to a group interlock with each other; and

said bipolar voltage circuit comprises;

a CMOS constituted by mutually connecting in series a source or a drain of an NMOS which is formed in a first substrate portion and is provided with a gate, and a source or a drain of a PMOS which is formed in a second substrate portion having a different conduction type from said first substrate portion and is provided with a gate, with a positive potential and a negative potential applied to two ends thereof at said PMOS side and at said NMOS side and an output potential extracted from a connection portion of said two MOS transistors;

a first means for voltage application that selectively applies said potential applied at said PMOS side and a first intermediate potential that is lower than said potential applied at said PMOS side and higher than said potential applied at said NMOS side to said gate of said PMOS; and

a second means for voltage application that selectively applies said potential applied at said NMOS side and a second intermediate potential higher than said potential applied at said NMOS side and lower than said potential applied at said PMOS side to said gate of said NMOS.