Enhanced blank check erase verify reference voltage source
First Claim
1. A reference voltage source for generating a predetermined reference voltage during a blank check operation, the circuit comprising:
- a first resistor connected between a first voltage source and an output node;
a second resistor having a first terminal connected to the output node; and
a reference voltage adjustment circuit connected between a second terminal of the second resistor and a second voltage source;
wherein said reference voltage adjustment circuit selectively connects the second resistor to the second voltage source through one or more of a plurality of resistive elements in response to one or more input signals such that a reference voltage at the output node is equal to the predetermined reference voltage.
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Accused Products
Abstract
A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage. The first and second resistors form a resistive divider that allows the predetermined reference voltage to track changes in the on-chip voltage source.
45 Citations
15 Claims
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1. A reference voltage source for generating a predetermined reference voltage during a blank check operation, the circuit comprising:
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a first resistor connected between a first voltage source and an output node; a second resistor having a first terminal connected to the output node; and a reference voltage adjustment circuit connected between a second terminal of the second resistor and a second voltage source; wherein said reference voltage adjustment circuit selectively connects the second resistor to the second voltage source through one or more of a plurality of resistive elements in response to one or more input signals such that a reference voltage at the output node is equal to the predetermined reference voltage. - View Dependent Claims (2, 3, 4, 5)
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6. A programmable logic device comprising:
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a programmable interconnect matrix including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each word line being connected to one of the bit lines through a memory cell; a blank check circuit connected to the bit lines for verifying that the plurality of memory cells are erased; a plurality of word line drivers, each word line driver generating a word line voltage on one of the plurality of word lines in response to an input voltage; and a reference voltage source for generating a predetermined reference voltage during a blank check operation, the reference voltage being utilized to generate the input voltage transmitted to the plurality of word line drivers, the reference voltage source comprising; a first resistor connected between a first voltage source and an output node; a second resistor having a first terminal connected to the output node; and a reference voltage adjustment circuit connected between a second terminal of the second resistor and a second voltage source; wherein said reference voltage adjustment circuit selectively connects the second resistor to the second voltage source through one or more of a plurality of resistive elements in response to one or more input signals such that a reference voltage at the output node is equal to the predetermined reference voltage. - View Dependent Claims (7, 8, 9, 10)
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11. A programmable logic device comprising:
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a function block including an AND array and a plurality of macrocells connected to receive product terms generated by the AND array, the AND array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each word line being connected to one of the bit lines through a memory cell; a blank check circuit connected to the bit lines for verifying that the plurality of memory cells are erased; a plurality of word line drivers, each word line driver generating a word line voltage on one of the plurality of word lines in response to an input voltage; and a reference voltage source for generating a predetermined reference voltage during a blank erase verify procedure, the reference voltage being utilized to generate the input voltage transmitted to the plurality of word line drivers, the reference voltage source comprising; a first resistor connected between a first voltage source and an output node; a second resistor having a first terminal connected to the output node; and a reference voltage adjustment circuit connected between a second terminal of the second resistor and a second voltage source; wherein said reference voltage adjustment circuit selectively connects the second resistor to the second voltage source through one or more of a plurality of resistive elements in response to one or more input signals such that a reference voltage at the output node is equal to the predetermined reference voltage. - View Dependent Claims (12, 13, 14, 15)
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Specification