Enhanced blank check erase verify reference voltage source

• US 5,898,618 A
• Filed: 01/23/1998
• Issued: 04/27/1999
• Est. Priority Date: 01/23/1998
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lakkapragada, Shankar, Curd, Derek R.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/012,677
• Time in Patent Office: 459 Days
• Field of Search: 365/185.22, 365/185.23, 365/185.29, 327/530, 327/538, 327/543
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage. The first and second resistors form a resistive divider that allows the predetermined reference voltage to track changes in the on-chip voltage source.

Claims

1. A reference voltage source for generating a predetermined reference voltage during a blank check operation, the circuit comprising:

a first resistor connected between a first voltage source and an output node;

a second resistor having a first terminal connected to the output node; and

a reference voltage adjustment circuit connected between a second terminal of the second resistor and a second voltage source;

wherein said reference voltage adjustment circuit selectively connects the second resistor to the second voltage source through one or more of a plurality of resistive elements in response to one or more input signals such that a reference voltage at the output node is equal to the predetermined reference voltage.

2. The reference voltage source according to claim 1, wherein the reference voltage adjustment circuit comprises:

a first resistive path connected between the second terminal of the second resistor and the second voltage source, the first resistive path including a first transistor that connects the first resistive path to the second voltage source in response to a first input signal; and

a second resistive path connected between the second terminal of the second resistor and the second voltage source, the second resistive path including a second transistor that connects the second resistive path to the second voltage source in response to a second input signal;

wherein the reference voltage at the output node is adjusted in response to the first and second input signals.

3. The reference voltage source according to claim 2,

wherein the first resistive path further comprises a first resistive element formed by a transistor having a first terminal and a gate connected to the second terminal of the second resistor, and a second resistive element formed by a transistor having a first terminal and a gate connected to a second terminal of the first resistive element, and a second terminal connected to the first transistor;

wherein the second resistive path further comprises a third resistive element formed by a transistor having a first terminal and a gate connected to the second terminal of the second resistor, and a second terminal connected to the second transistor; and

wherein each of the first resistive element and the second resistive element has a larger width-to-length ratio than that of the third resistive element.

4. The reference voltage source according to claim 3, wherein the reference voltage adjustment circuit further comprises:

a third resistive path connected between the second terminal of the second resistor and the second voltage source, the third resistive path including a third transistor that connects the third resistive path to the second voltage source in response to a third input signal, the third resistive path also including;

a fourth resistive element formed by a transistor having a first terminal, a second terminal and a gate, the first terminal and the gate being connected to the second terminal of the second resistor; and

a fifth resistive element formed by a transistor having a first terminal, a second terminal and a gate, the first terminal and the gate being connected to the second terminal of the fourth resistive element, and the second terminal being connected to the third transistor;

wherein the third, fourth and fifth resistive elements have an equal resistance.

5. The reference voltage source according to claim 4, further comprising:

a fourth resistive path connected between the second terminal of the second resistor and the second voltage source, the fourth resistive path including a fourth transistor that connects the fourth resistive path to the second voltage source in response to a fourth input signal;

wherein the fourth resistive path further includes a sixth resistive element, an seventh resistive element and an eighth resistive element connected in series between the second resistor and the fourth transistor, each of the sixth resistive element, the seventh resistive element and the eighth resistive element being formed by a transistor having a gate connected to the fourth resistive path; and

wherein the fourth transistor has a width-to-length ratio that is equal to that of each of the second and third transistors; and

wherein each of the sixth, seventh and eighth resistive elements has a width-to-length ratio that is equal to that of each of the third, fourth and fifth resistive elements.

6. A programmable logic device comprising:

a programmable interconnect matrix including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each word line being connected to one of the bit lines through a memory cell;

a blank check circuit connected to the bit lines for verifying that the plurality of memory cells are erased;

a plurality of word line drivers, each word line driver generating a word line voltage on one of the plurality of word lines in response to an input voltage; and

a reference voltage source for generating a predetermined reference voltage during a blank check operation, the reference voltage being utilized to generate the input voltage transmitted to the plurality of word line drivers, the reference voltage source comprising;

a first resistor connected between a first voltage source and an output node;

a second resistor having a first terminal connected to the output node; and

a reference voltage adjustment circuit connected between a second terminal of the second resistor and a second voltage source;

wherein said reference voltage adjustment circuit selectively connects the second resistor to the second voltage source through one or more of a plurality of resistive elements in response to one or more input signals such that a reference voltage at the output node is equal to the predetermined reference voltage.

7. The programmable logic device according to claim 6, wherein the reference voltage adjustment circuit of the reference voltage source further comprises:

a first resistive path connected between the second terminal of the second resistor and the second voltage source, the first resistive path including a first transistor that connects the first resistive path to the second voltage source in response to a first input signal; and

a second resistive path connected between the second terminal of the second resistor and the second voltage source, the second resistive path including a second transistor that connects the second resistive path to the second voltage source in response to a second input signal;

wherein the reference voltage at the output node is adjusted in response to the first and second input signals.

8. The programmable logic device according to claim 7,

wherein the first resistive path further comprises a first resistive element formed by a transistor having a first terminal and a gate connected to the second terminal of the second resistor, and a second resistive element formed by a transistor having a first terminal and a gate connected to a second terminal of the first resistive element, and a second terminal connected to the first transistor;

wherein the second resistive path further comprises a third resistive element formed by a transistor having a first terminal and a gate connected to the second terminal of the second resistor, and a second terminal connected to the second transistor; and

wherein each of the first resistive element and the second resistive element has a larger width-to-length ratio than that of the third resistive element.

9. The programmable logic device according to claim 8, wherein the reference voltage adjustment circuit further comprises:

a third resistive path connected between the second terminal of the second resistor and the second voltage source, the third resistive path including a third transistor that connects the third resistive path to the second voltage source in response to a third input signal, the third resistive path also including;

a fourth resistive element formed by a transistor having a first terminal, a second terminal and a gate, the first terminal and the gate being connected to the second terminal of the second resistor; and

a fifth resistive element formed by a transistor having a first terminal, a second terminal and a gate, the first terminal and the gate being connected to the second terminal of the fourth resistive element, and the second terminal being connected to the third transistor; and

wherein the third, fourth and fifth resistive elements have an equal resistance.

10. The programmable logic device according to claim 9, further comprising:

a fourth resistive path connected between the second terminal of the second resistor and the second voltage source, the fourth resistive path including a fourth transistor that connects the fourth resistive path to the second voltage source in response to a fourth input signal;

wherein the fourth resistive path further includes a sixth resistive element, an seventh resistive element and an eighth resistive element connected in series between the second resistor and the fourth transistor, each of the sixth resistive element, the seventh resistive element and the eighth resistive element being formed by a transistor having a gate connected to the fourth resistive path; and

wherein the fourth transistor has a width-to-length ratio that is equal to that of each of the second and third transistors; and

wherein each of the sixth, seventh and eighth resistive elements has a width-to-length ratio that is equal to that of each of the third, fourth and fifth resistive elements.

11. A programmable logic device comprising:

a function block including an AND array and a plurality of macrocells connected to receive product terms generated by the AND array, the AND array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each word line being connected to one of the bit lines through a memory cell;

a blank check circuit connected to the bit lines for verifying that the plurality of memory cells are erased;

a plurality of word line drivers, each word line driver generating a word line voltage on one of the plurality of word lines in response to an input voltage; and

a reference voltage source for generating a predetermined reference voltage during a blank erase verify procedure, the reference voltage being utilized to generate the input voltage transmitted to the plurality of word line drivers, the reference voltage source comprising;

a first resistor connected between a first voltage source and an output node;

a second resistor having a first terminal connected to the output node; and

a reference voltage adjustment circuit connected between a second terminal of the second resistor and a second voltage source;

wherein said reference voltage adjustment circuit selectively connects the second resistor to the second voltage source through one or more of a plurality of resistive elements in response to one or more input signals such that a reference voltage at the output node is equal to the predetermined reference voltage.

12. The programmable logic device according to claim 11, wherein the reference voltage adjustment circuit of the reference voltage source further comprises:

a first resistive path connected between the second terminal of the second resistor and the second voltage source, the first resistive path including a first transistor that connects the first resistive path to the second voltage source in response to a first input signal; and

a second resistive path connected between the second terminal of the second resistor and the second voltage source, the second resistive path including a second transistor that connects the second resistive path to the second voltage source in response to a second input signal;

wherein the reference voltage at the output node is adjusted in response to the first and second input signals.

13. The programmable logic device according to claim 12,

wherein the first resistive path further comprises a first resistive element formed by a transistor having a first terminal and a gate connected to the second terminal of the second resistor, and a second resistive element formed by a transistor having a first terminal and a gate connected to a second terminal of the first resistive element, and a second terminal connected to the first transistor;

wherein the second resistive path further comprises a third resistive element formed by a transistor having a first terminal and a gate connected to the second terminal of the second resistor, and a second terminal connected to the second transistor; and

wherein each of the first resistive element and the second resistive element has a larger width-to-length ratio than that of the third resistive element.

14. The programmable logic device according to claim 13, wherein the reference voltage adjustment circuit further comprises:

a third resistive path connected between the second terminal of the second resistor and the second voltage source, the third resistive path including a third transistor that connects the third resistive path to the second voltage source in response to a third input signal, the third resistive path also including;

a fourth resistive element formed by a transistor having a first terminal, a second terminal and a gate, the first terminal and the gate being connected to the second terminal of the second resistor; and

a fifth resistive element formed by a transistor having a first terminal, a second terminal and a gate, the first terminal and the gate being connected to the second terminal of the fourth resistive element, and the second terminal being connected to the third transistor; and

wherein the third, fourth and fifth resistive elements have an equal resistance.

15. The programmable logic device according to claim 14, further comprising:

a fourth resistive path connected between the second terminal of the second resistor and the second voltage source, the fourth resistive path including a fourth transistor that connects the fourth resistive path to the second voltage source in response to a fourth input signal;

wherein the fourth resistive path further includes a sixth resistive element, an seventh resistive element and an eighth resistive element connected in series between the second resistor and the fourth transistor, each of the sixth resistive element, the seventh resistive element and the eighth resistive element being formed by a transistor having a gate connected to the fourth resistive path; and

wherein the fourth transistor has a width-to-length ratio that is equal to that of each of the second and third transistors; and

wherein each of the sixth, seventh and eighth resistive elements has a width-to-length ratio that is equal to that of each of the third, fourth and fifth