Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array

• US 5,898,776 A
• Filed: 11/21/1996
• Issued: 04/27/1999
• Est. Priority Date: 11/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Eaton, David D., Chan, Andrew K., Apland, James M.
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US08/754,461
• Time in Patent Office: 887 Days
• Field of Search: 380/3, 380/4, 326/39-41
• US Class Current: 326/8
• CPC Class Codes: G01R 31/31702 Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test

Abstract

A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.

Claims

1. A field programmable gate array, comprising:

a plurality of modules;

a plurality of first antifuses of a programmable interconnect structure, selected ones of said first antifuses being programmed, said first antifuses being programmable to interconnect selected ones of said logic modules;

a plurality of second antifuses, selected ones of said second antifuses being programmed, said second antifuses not being programmable to interconnect said logic modules and not being part of the programmable interconnect structure; and

means for preventing first data indicative of which ones of said first antifuses are programmed from being extracted from said field programmable gate array while second data indicative of which ones of said second antifuses are programmed is extracted from said field programmable gate array.

2. The field programmable gate array of claim 1, wherein said second data indicative of which ones of said second antifuses are programmed is extractable by imposing a voltage across one of said second antifuses and determining whether a current flows into said field programmable gate array, through said second antifuse, and out of said field programmable gate array, and then repeating said imposing and said determining for each other of said second antifuses.

3. The field programmable gate array of claim 1, wherein said means for preventing includes:

means for preventing said first data from being extracted from said field programmable gate array if said means is in a programmed state said means being a security antifuse.

4. The field programmable gate array of claim 1, further comprising:

a first programming control shift register capable of driving a voltage onto first programming conductors extending in a first direction; and

a second programming control shift register capable of driving a voltage onto second programming conductors extending in a second direction perpendicular to said first direction, said means preventing shifting of said second programming control shift register but not preventing shifting of said first programming control shift register.

5. The field programmable gate array of claim 4, wherein said first programming control shift register controls a first plurality of programming control conductors, each of said first plurality of programming control conductors extending in said first direction, and wherein said second programming control shift register controls a second plurality of programming control conductors, each of said second plurality of programming control conductors extending in said second direction.

6. The field programmable gate array of claim 1 having a plurality of terminals, said means for preventing comprising:

a security antifuse; and

means for enabling a programming current to flow through said security antifuse when a first combination of digital values is present on said plurality of terminals of said field programmable gate array, and for preventing a programming current from flowing through said security antifuse when other combinations of digital values are present on said plurality of terminals of said field programmable gate array.

7. The field programmable gate array of claim 6, wherein said means for enabling a programming current comprises:

a programming pass transistor disposed in parallel with said security antifuse; and

a decoder having a plurality of input leads and an output lead, said input leads being coupled to said plurality of terminals, said output lead being coupled to a gate of said programming pass transistor.

8. The field programmable gate array of claim 1, further comprising:

a shift register, said means for preventing gating a clock signal and thereby blocking said clock signal from clocking said shift register.

9. A field programmable gate array, comprising:

a boundary scan register; and

a boundary scan disable circuit preventing information in said boundary scan register from being shifted out of said field programmable gate array when a security antifuse of said boundary scan disable circuit is in a programmed state.

10. The field programmable gate array of claim 9, further comprising:

a bypass register, programming of said security antifuse not preventing shifting of said bypass register.

11. The field programmable gate array of claim 9, wherein said boundary scan disable circuit has an output lead which is coupled to an input lead of said boundary scan register, a predetermined digital value being present on said output lead of said disable circuit if said security antifuse is in a programmed state.

12. The field programmable gate array of claim 11, wherein said boundary scan disable circuit prevents information in said boundary scan register from being shifted out of said field programmable gate array by gating a clock signal supplied to said boundary scan shift register.

13. The field programmable gate array of claim 9, further comprising:

a plurality of logic modules, each of said logic modules having a sequential logic element with a scan path, said scan paths of said sequential logic elements being chained together to form a logic module scan path.

14. The field programmable gate array of claim 13, wherein said boundary scan register comprises an input multiplexer, a data input lead of said input multiplexer being coupled to said logic module scan path such that information in said sequential logic elements of said logic modules can be shifted through said boundary scan register.

15. The field programmable gate array of claim 9, further comprising:

a plurality of interface cells, each of said interface cells having a sequential logic element with a scan path, said scan paths of said sequential logic elements of said interface cells being chained together to form an interface cell scan path.

16. The field programmable gate array of claim 15, wherein said boundary scan register comprises an input multiplexer, a data input lead of said input multiplexer being coupled to said interface cell scan path such that information in said sequential logic elements of said interface cells can be shifted through said boundary scan register.

17. The field programmable gate array of claim 9 having a plurality of terminals, said boundary scan disable circuit comprising:

said security antifuse;

a decoder having input leads and an output lead, said input leads being coupled to said plurality of terminals of said field programmable gate array; and

a programming circuit for programming said security antifuse, said programming circuit having an input lead coupled to said output lead of said decoder.

18. A field programmable gate array, comprising:

a bypass register;

a logic module scan path extending through a plurality of logic modules;

a terminal;

a security antifuse not usable to interconnect logic modules; and

means for preventing, when said security antifuse is in a programmed state, information in said logic module scan path from being shifted out of said field programmable gate array onto said terminal but not preventing information in said bypass register from being shifted through said bypass register and out of said field programmable gate array onto said terminal.

19. The field programmable gate array of claim 18, further comprising:

a plurality of terminals; and

means for programming said security antifuse when a predetermined combination of digital values are present on said plurality of terminals.