Method and system for PCMCIA card boot from dual-ported memory

• US 5,898,869 A
• Filed: 09/20/1996
• Issued: 04/27/1999
• Est. Priority Date: 09/20/1996
• Status: Expired due to Term

• Current Assignee: Schneider Electric Systems USA, Inc. (Schneider Electric SE)
• Original Assignee: The Foxboro Company (Schneider Electric SE)
• Inventors: Anderson, Daniel Joseph
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US08/716,983
• Time in Patent Office: 949 Days
• Field of Search: 395/651, 395/652, 395/653
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A PCMCIA card includes a processor and a dual-ported memory thereon. The PCMCIA card is plugged into a host, such that both the PCMCIA card'"'"'s processor and the host have access to the dual-ported memory. Upon initialization, the host will load the dual-ported memory will a boot sequence for the processor on the PCMCIA card. The processor on the PCMCIA card is then released from a reset state, and proceeds to boot from the boot sequence loaded by the host. The processor on the PCMCIA card is released from reset by the host accessing a predetermined location within the address space of the PCMCIA card.

Claims

1. A PCMCIA card comprising:

a processor configured to boot by executing instructions at a boot location;

a memory coupled to said processor, said memory containing said boot location and containing a memory integrity checking program for a region of a non-volatile memory within said PCMCIA card, and containing instructions to transfer program execution to code within said non-volatile memory after successful completion of said integrity checking;

a PCMCIA interface circuit configured to couple said PCMCIA card to a host computer, said PCMCIA interface circuit being coupled to said memory such that both said host and said processor have access to said memory when said PCMCIA card is coupled to said host;

reset logic configured to reset said PCMCIA card and suspend processor execution; and

boot logic configured to release said suspended processor execution and begin said processor booting at said boot location.

2. The PCMCIA card of claim 1, further comprising processor control logic coupled to said reset logic, said boot logic and a reset line of said processor, said processor control logic configured to activate said reset line in response to said reset logic and deactivate said reset line in response to said boot logic.

3. The PCMCIA card of claim 2, wherein said processor control logic includes a flip-flop.

4. The PCMCIA card of claim 3, wherein said flip-flop comprises a logic function within a programmable logic device.

5. The PCMCIA card of claim 1, wherein said reset logic is coupled to a reset output of said PCMCIA interface that is responsive to both a hard and a soft reset initiated by said host.

6. The PCMCIA card of claim 5, wherein said PCMCIA interface includes a single-chip PCMCIA interface, and wherein said reset logic comprises a portion of said single-chip-PCMCIA interface that drives said reset output thereof.

7. The PCMCIA card of claim 1, wherein said boot logic is coupled to an address bus received from said host.

8. The PCMCIA card of claim 7, wherein said boot logic includes address decode circuitry responsive to a particular address presented by said host for releasing said suspended processor execution and causing said processor to boot.

9. The PCMCIA card of claim 8, wherein said PCMCIA interface includes a single-chip PCMCIA interface and said address decode circuitry comprises programmable chip select logic within said single-chip PCMCIA interface.

10. The PCMCIA card of claim 1, wherein said memory comprises a dual-ported memory.

11. The PCMCIA card of claim 10, wherein said dual-ported memory includes at least one semaphore register such that said dual-ported memory facilitates both booting of said processor and communications between said processor and said host.

12. The PCMCIA card of claim 11, further comprising address decode circuitry coupled to said dual-ported memory such that each of a memory space of said dual-ported memory and a semaphore space of said dual-ported memory are mapped into different memory regions of said processor.

13. The PCMCIA card of claim 1, wherein said memory comprises a bootable memory.

14. The PCMCIA card of claim 13, wherein said non-volatile memory comprises a FLASH memory.

15. The PCMCIA card of claim 1, wherein said memory comprises a bootable memory and said PCMCIA card further comprising a volatile memory coupled to said processor.

16. A method for operating a PCMCIA card, said PCMCIA card including a processor and a memory coupled to said processor, said PCMCIA card being mechanically and electrically coupled to a host such that said memory is coupled to said host, said method comprising:

(a) resetting said PCMCIA card, said resetting suspending execution of said processor;

(b) downloading code from said host into said memory of said PCMCIA card; and

(c) releasing said suspended processor and causing it to boot using said downloaded code, wherein said downloaded code includes diagnostic routines which check an integrity of a non-volatile memory within the PCMCIA card upon said boot, and transfers processor execution to code within said non-volatile memory if said integrity is good.

17. The method of claim 16, wherein said resetting and said releasing are initiated by separate mechanisms.

18. The method of claim 17, wherein resetting comprises asserting a hardware reset signal.

19. The method of claim 18, wherein said hardware reset signal results from a power-on reset.

20. The method of claim 17, wherein said resetting includes said host sending a software reset signal.

21. The method of claim 17, wherein said releasing includes said host accessing an address, said accessing being decoded within said PCMCIA card, thereby causing said releasing said suspended processor and causing it to boot using said downloaded code.

22. The method of claim 16, wherein said memory comprises a bootable memory, said PCMCIA card includes a writeable memory coupled to said processor, and said code includes a loader routine such that said method further includes loading said writeable memory from said host through execution of said loader routine.

23. The method of claim 22, wherein said writeable memory comprises non-volatile memory.

24. The method of claim 22, wherein said writeable memory comprises FLASH memory.

25. The method of claim 24, further comprising passing information between said host and said processor of said PCMCIA card through said bootable memory.

26. The method of claim 25, wherein said bootable memory comprises a dual-ported memory having at least one semaphore register therein, said method including exchanging information between said host and said processor of said PCMCIA card using said at least one semaphore register.

27. A method for operating a PCMCIA card, said PCMCIA card including a processor and a memory coupled to said processor, said PCMCIA card being mechanically and electrically coupled to a host through a PCMCIA interface, such that said memory is coupled to said host, said method comprising:

(a) transmitting a reset signal from said host to said PCMCIA card, through said PCMCIA interface, said reset signal resetting said PCMCIA card and thereafter, leaving said processor in a suspended state and said memory in an active state;

(b) transferring a program from said host to said PCMCIA Card through said PCMCIA interface while said processor is suspended, said program including a memory integrity checking program for a region of a non-volatile memory within said PCMCIA card, and instructions to transfer program execution to code within said non-volatile memory after successful completion of said integrity checking,

(c) transmitting a release signal from said host to said PCMCIA card, through said PCMCIA interface; and

(d) said processor beginning execution of said program in response to said release signal.

28. The method of claim 27, wherein said transmitting a reset signal includes asserting a hardware reset line of said PCMCIA interface.

29. The method of claim 28, wherein said transmitting a release signal comprises said host accessing a predetermined memory location.

30. A PCMCIA card in an operational state, said PCMCIA card comprising:

a processor in a suspended state, said processor configured to boot by executing instruction at a boot location upon exiting said suspended state,

a dual-ported RAM in an active state, said dual-ported RAM being coupled to said processor and containing a program beginning at said boot location, said program including a memory integrity checking program for a region of a non-volatile memory within said PCMCIA card, and instructions to transfer program execution to code within said non-volatile memory after successful completion of said integrity checking; and

a PCMCIA interface coupled to said dual-ported RAM to facilitate access thereto by a host.