Fabrication of semiconductor structure having two levels of buried regions

• US 5,899,714 A
• Filed: 06/06/1995
• Issued: 05/04/1999
• Est. Priority Date: 08/18/1994
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Merrill, Richard B., Saha, Samar, Brehmer, Kevin E., Gadepally, Kamesh, Cacharelis, Philip J., Farrenkopf, Douglas R.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/471,061
• Time in Patent Office: 1,428 Days
• Field of Search: 257/552, 257/565, 257/593, 257/655, 257/657, 257/370, 257/378, 257/544, 257/545, 257/549, 438/FOR 235, 438/FOR 237, 438/FOR 219, 438/FOR 160, 438/202, 438/220, 438/416, 438/208, 438/358, 148/DIG. 85
• US Class Current: 438/202
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: Y10S 148/085 Isolated-integrated

Abstract

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Claims

1. A method comprising the steps of:

introducing first and second semiconductor dopants of opposite conductivity types selectively into a monocrystalline semiconductive substrate through an upper surface of the substrate;

providing a lower monocrystalline semiconductive layer over the substrate such that (a) the lower semiconductive layer adjoins the substrate along a lower semiconductor interface and (b) the first and second dopants respectively form first and second lower buried regions of opposite conductivity types along the lower semiconductor interface;

introducing third and fourth semiconductor dopants of opposite conductivity types selectively into the lower semiconductive layer through an upper surface of the lower semiconductive layer;

providing an upper monocrystalline semiconductive layer over the lower semiconductive layer such that (a) the upper semiconductive layer adjoins the lower semiconductive layer along an upper semiconductor interface and (b) the third and fourth dopants respectively form third and fourth buried regions of opposite conductivity types along the upper semiconductor interface; and

introducing at least one semiconductor dopant selectively into the upper semiconductive layer through an upper surface of the upper semiconductive layer to define a plurality of P-type device regions and a plurality of N-type device regions such that one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type and vertically extends into the upper semiconductive layer to a depth sufficient to meet one of the upper buried regions.

2. A method as in claim 1 wherein:

the first and second dopants diffuse only partway through the substrate and the lower semiconductive layer during the two providing steps; and

the third dopant diffuses only partway through each semiconductive layer during the second-mentioned providing step.

3. A method as in claim 2 wherein the first and second dopants are introduced into the substrate at locations sufficiently apart from each other that the two lower buried regions are spaced laterally apart from each other along the lower semiconductor interface.

4. A method as in claim 2 further including the step of introducing semiconductor dopants selectively into the P-type and N-type device regions to form transistor zones.

5. A method as in claim 2 wherein the dopants are introduced into the substrate and the upper and lower semiconductive layers at such locations that at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate.

6. A method as in claim 5 wherein each so-isolated device region, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded within the upper and lower semiconductive layers and the substrate by semiconductive material of opposite conductivity type to that so-isolated device region.

7. A method as in claim 6 wherein semiconductive material directly surrounding one of the so-isolated device regions comprises (a) another of the device regions, (b) one of the upper buried regions, and (c) one of the lower buried regions connected through the lower semiconductive layer to said one upper buried region.

8. A method as in claim 5 wherein one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded within the upper and lower semiconductive layers and the substrate by a tub of opposite conductivity type to that so-isolated device region, the tub being surrounded within the upper and lower semiconductive layers and the substrate by semiconductive material of opposite conductivity type to the tub.

9. A method as in claim 8 wherein:

the tub comprises (a) another of the device regions and (b) one of the upper buried regions; and

semiconductive material directly surrounding the tub comprises (a) a further one of the device regions and (b) one of the lower buried regions.

10. A method as in claim 7 wherein:

the first and second dopants diffuse only partway through the substrate and the lower semiconductive layer during the two providing steps; and

the third and fourth dopants diffuse only partway through each semiconductive layer during the second-mentioned providing step.

11. A method as in claim 10 wherein:

the first and second dopants are introduced into the substrate at locations sufficiently apart from each other that the two lower buried regions are spaced laterally apart from each other along the lower semiconductor interface; and

the third and fourth dopants are introduced into the lower semiconductive layer at locations sufficiently apart from each other that the two upper buried regions are spaced laterally apart from each other along the upper semiconductor interface.

49. A method as in claim 2 wherein each device region vertically extends largely through the upper semiconductive layer.

50. A method as in claim 49 wherein the step of introducing at least one dopant to define the device regions comprises introducing semiconductor dopants of opposite conductivity types selectively into the upper semiconductive layer to define the P-type and N-type device regions.

51. A method as in claim 10 wherein each device region vertically extends largely through the upper semiconductive layer.

52. A method as in claim 51 wherein the step of introducing at least one dopant to define the device regions comprises introducing semiconductor dopants of opposite conductivity types selectively into the upper semiconductive layer to define the P-type and N-type device regions.

12. A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

introducing first semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;

introducing second semiconductor dopant of the second conductivity type into the major region to define a first lateral isolation region of the second conductivity type continuous with the vertical isolation region, the second dopant having a greater diffusivity than the first dopant; and

forming (a) a semiconductive layer over the major region such that part of each of the first and second dopants diffuses into the semiconductor layer to expand the vertical and first lateral isolation regions into the semiconductive layer and (b) a transistor from material of the semiconductive layer overlying the vertical isolation region, the second dopant diffusing further into the semiconductive layer than the first dopant whereby the first lateral isolation region expands into the semiconductive layer to provide at least partial lateral junction isolation for the transistor while the vertical isolation region expands into the semiconductive layer to at least partially isolate the transistor from first conductivity type material of the major region.

13. A method as in claim 12 further including the step of providing the semiconductive layer with an additional lateral isolation region of the second conductivity type meeting the first lateral isolation region such that the vertical and two lateral isolation regions completely isolate the transistor from the first conductivity type material of the major region.

14. A method as in claim 12 wherein the transistor is a bipolar transistor whose base is of the second conductivity type.

15. A method as in claim 14 further including, prior to the step of forming the semiconductive layer and the transistor, the step of introducing dopant of the first conductivity type into the major region to define a more heavily doped region of the first conductivity type laterally encircled by the first lateral isolation region, part of the dopant of the first conductivity type diffusing into the semiconductive layer during formation of the semiconductive layer and the transistor such that the dopant of the first conductivity type diffuses further into the semiconductive layer than the first dopant of the second conductivity type, a buffer region of the first conductivity type thereby being created by expansion of the more heavily doped region into the semiconductive layer so that the buffer region overlies the vertical isolation region and is encircled by the first lateral isolation region.

16. A method as in claim 14 further including the step of forming in the structure a bipolar transistor whose base is of the first conductivity type and which is laterally separated from the first lateral isolation region by a region of the first conductivity type.

17. A method as in claim 14 further including the steps of:

forming in the structure a first field-effect transistor ("FET") having source/drain zones of the first conductivity type, the first FET being separated from the first lateral isolation region by a region of the first conductivity type; and

forming in the structure a second FET having source/drain zones of the second conductivity type, the second FET being separated from the bipolar transistor by the first lateral isolation region.

18. A method as in claim 14 wherein the step of forming the semiconductive layer and the transistor entails:

forming a lower semiconductive layer that includes (a) a first collector zone of the bipolar transistor, the first collector zone being of the first conductivity type and overlying the vertical isolation region, and (b) a second lateral isolation region of the second conductivity type meeting the first lateral isolation region and surrounding the first collector zone; and

forming an upper semiconductive layer over the lower layer, the upper layer including (a) a second collector zone of the bipolar transistor, the second collector zone being of the first conductivity type and being continuous with the first collector zone, (b) base and emitter zones of the bipolar transistor, and (c) a third lateral isolation region of the second conductivity type meeting the second lateral isolation region and laterally surrounding the second collector zone.

42. A method as in claim 12 wherein the transistor is spaced vertically apart from the major region by at least the vertical isolation region.

43. A method as in claim 12 wherein both lateral isolation regions laterally surround the transistor.

44. A method as in claim 12 wherein the forming step entails introducing at least on e dopant of the first conductivity type into the semiconductive layer to define a specified region of the first conductivity type laterally surrounded by both lateral isolation regions and meeting the vertical isolation region.

19. A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;

forming a lower semiconductive layer over the major region so that the vertical isolation region updiffuses partway through the lower layer and so that first semiconductor dopant of the first conductivity type enters the lower layer to form a buffer region of the first conductivity type over the vertical isolation region;

introducing second semiconductor dopant of the first conductivity type into the lower layer to form over the buffer region a first collector zone of the first conductivity type for a first vertical bipolar transistor;

forming an upper semiconductive layer over the lower layer;

providing a second collector zone of the first conductivity type in the upper layer such that the second collector zone meets the first collector zone; and

providing the first bipolar transistor with a base zone of the second conductivity type and an emitter zone of the first conductivity type.

20. A method as in claim 19 wherein:

the step of forming the lower layer entails providing the lower layer with a third collector zone of the second conductivity type for a second vertical bipolar transistor;

the step of forming the upper layer entails providing the upper layer with a fourth collector zone of the second conductivity type for the second vertical bipolar transistor; and

the method further includes the step of providing the second bipolar transistor with a base zone of the first conductivity type and an emitter zone of the second conductivity type.

21. A method as in claim 20 wherein:

the step of forming the lower layer further includes providing the lower layer with a first P-type region and a first N-type region;

the step of forming the upper layer further includes (a) providing the upper layer with a second P-type region that meets, and has a lower net dopant concentration than, the first P-type region and (b) providing the upper layer with a second N-type region that meets, and has a lower net dopant concentration than, the first N-type region; and

the method further includes the steps of forming gate insulation over the second P-type region and the second N-type region, forming a gate electrode above the gate insulation over the second P-type region, forming a gate electrode above the gate insulation over the second N-type region, forming N-type source/drain zones in the second P-type region, and forming P-type source/drain zones in the second N-type region.

22. A method as in claim 19 wherein:

the step of forming the upper layer entails providing the upper layer with a body region for a field-effect transistor ("FET"); and

the method further includes the steps of forming gate insulation over the body region, forming a gate electrode over the gate insulation, and providing the body region with source/drain zones for the FET.

23. A method as in claim 22 wherein the step of forming the lower layer entails providing the lower layer with a buried region that meets, is of the same conductivity type as, and has a higher net dopant concentration than, the body region.

53. A method as in claim 19 wherein the first dopant of the first conductivity type enters the lower layer by diffusion from the major region into which the first dopant of the first conductivity type is introduced before the lower layer is formed.

54. A method as in claim 53 wherein the buffer region has a lower net peak dopant concentration than the first collector zone.

24. A method comprising the steps of:

forming a semiconductor structure that comprises (a) a monocrystalline semiconductive substrate, (b) a lower monocrystalline semiconductive layer provided over the substrate such that the lower semiconductive layer adjoins the substrate along a lower semiconductor interface, and (c) an upper monocrystalline semiconductive layer provided over the lower semiconductive layer such that the upper semiconductive layer adjoins the lower semiconductive layer along an upper semiconductor interface;

introducing (a) first and second semiconductor dopants of opposite conductivity types into semiconductive material of the structure to respectively form first and second lower buried regions of opposite conductivity types along the lower semiconductor interface and (b) third and fourth semiconductor dopants of opposite conductivity types into semiconductive material of the structure to respectively form first and second upper buried regions of opposite conductivity types along the upper semiconductor interface; and

introducing at least one semiconductor dopant selectively into the upper semiconductive layer to define a plurality of P-type device regions and a plurality of N-type device regions such that one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type and vertically extends into the upper semiconductive layer to a depth sufficient to meet one of the upper buried regions.

25. A method as in claim 24 wherein:

the first and second dopants diffuse only partway through the substrate and the lower semiconductive layer during the forming and introducing steps; and

the third and fourth dopants diffuse only partway through each semiconductive layer during the forming and introducing steps.

26. A method as in claim 25 wherein:

the first and second dopants are introduced into semiconductive material of the structure at locations sufficiently apart from each other that the two lower buried regions are spaced laterally apart from each other along the lower semiconductor interface; and

the third and fourth dopants are introduced into semiconductive material of the structure at locations sufficiently apart from each other that the two upper buried regions are spaced laterally apart from each other along the upper semiconductor interface.

27. A method as in claim 24 further including the step of introducing semiconductor dopants selectively into the P-type and N-type device regions to form transistor zones.

28. A method as in claim 24 wherein the dopants are introduced into the structure at such locations that at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate.

29. A method as in claim 28 wherein each so-isolated device region, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded within the structure by semiconductive material of opposite conductivity type to that so-isolated device region.

30. A method as in claim 29 wherein semiconductive material directly surrounding one of the so-isolated device regions comprises (a) another of the device regions, (b) one of the upper buried regions, and (c) one of the lower buried regions connected through the lower semiconductive layer to said one upper buried region.

31. A method as in claim 28 wherein one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, is surrounded within the structure by a tub of opposite conductivity type to that so-isolated device region, the tub being surrounded within the structure by semiconductive material of opposite conductivity type to the tub.

32. A method as in claim 31 wherein:

the tub comprises (a) another of the device regions and (b) one of the upper buried regions; and

semiconductive material directly surrounding the tub comprises (a) a further one of the device regions and (b) and one of the lower buried regions.

55. A method as in claim 24 wherein each device region vertically extends largely through the upper semiconductive layer.

56. A method as in claim 55 wherein the step of introducing at least one dopant to define the device regions comprises introducing semiconductor dopants of opposite conductivity types selectively into the upper semiconductive layer to define the P-type and N-type device regions.

33. A method comprising the steps of:

introducing first and second semiconductor dopants of opposite conductivity types selectively into a monocrystalline semiconductive substrate;

providing a lower monocrystalline semiconductive layer over the substrate such that (a) the lower semiconductive layer adjoins the substrate along a lower semiconductor interface and (b) the first and second dopants respectively form first and second lower buried regions of opposite conductivity types along the lower semiconductor interface;

introducing third semiconductor dopant of a selected conductivity type selectively into the lower semiconductive layer;

providing an upper monocrystalline semiconductive layer over the lower semiconductive layer such that (a) the upper semiconductive layer adjoins the lower semiconductive layer along the upper semiconductor interface and (b) the third dopant forms an upper buried region of the selected conductivity type along the upper semiconductor interface; and

introducing semiconductor dopants of opposite conductivity types selectively into the upper semiconductive layer to define a plurality of P-type device regions and a plurality of N-type device regions such that one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type, each device region vertically extending largely through the upper semiconductive layer, the dopants being introduced into the substrate and the upper and lower semiconductive layers at such locations that at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate, one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, being surrounded within the upper and lower semiconductive layers and the substrate by semiconductive material which is of opposite conductivity type to that so-isolated device region and which comprises (a) another of the device regions, (b) the upper buried region, and (c) one of the lower buried regions connected through the lower semiconductive layer to the upper buried region.

34. A method as in claim 33 wherein:

the first and second dopants diffuse only partway through the substrate and the lower semiconductive layer during the two providing steps; and

the third dopant diffuses only partway through each semiconductive layer during the second-mentioned providing step.

35. A method as in claim 33 wherein the first and second dopants are introduced into the substrate at locations sufficiently apart from each other that the two lower buried regions are spaced laterally apart from each other along the lower semiconductor interface.

36. A method as in claim 33 further including the step of introducing semiconductor dopants selectively into the P-type and N-type device regions to form transistor zones.

37. A method comprising the steps of:

introducing first and second semiconductor dopants of opposite conductivity types selectively into a monocrystalline semiconductive substrate;

providing a lower monocrystalline semiconductive layer over the substrate such that (a) the lower semiconductive layer adjoins the substrate along a lower semiconductor interface and (b) the first and second dopants respectively form first and second lower buried regions of opposite conductivity types along the lower semiconductor interface;

introducing third semiconductor dopant of a selected conductivity type selectively into the lower semiconductive layer;

providing an upper monocrystalline semiconductive layer over the lower semiconductive layer such that (a) the upper semiconductive layer adjoins the lower semiconductive layer along the upper semiconductor interface and (b) the third dopant forms an upper buried region of the selected conductivity type along the upper semiconductor interface; and

introducing semiconductor dopants of opposite conductivity types selectively into the upper semiconductive layer to define a plurality of P-type device regions and a plurality of N-type device regions, each device region extending largely through the upper semiconductive layer, the dopants being introduced into the substrate and the upper and lower semiconductive layers at such locations that at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate, one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, being surrounded within the upper and lower semiconductive layers and the substrate by a tub of opposite conductivity type to that device region, the tub being surrounded within the upper and lower semiconductive layers and the substrate by semiconductive material of opposite conductivity type to the tub.

38. A method as in claim 37 wherein:

the first and second dopants diffuse only partway through the substrate and the lower semiconductive layer during the two providing steps; and

the third dopant diffuses only partway through each semiconductive layer during the second-mentioned providing step.

39. A method as in claim 37 wherein the first and second dopants are introduced into the substrate at locations sufficiently apart from each other that the two lower buried regions are spaced laterally apart from each other along the lower semiconductor interface.

40. A method as in claim 37 further including the step of introducing semiconductor dopants selectively into the P-type and N-type device regions to form transistor zones.

41. A method as in claim 37 wherein:

the tub comprises (a) another of the device regions and (b) the upper buried region; and

semiconductive material directly surrounding the tub comprises (a) a further one of the device regions and (b) one of the lower buried regions.

57. A method as in claim 37 wherein one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type.

45. A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

introducing first semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;

introducing second semiconductor dopant of the second conductivity type into the major region to define a first lateral isolation region of the second conductivity type continuous with the vertical isolation region, the second dopant having a greater diffusivity than the first dopant;

introducing dopant of the first conductivity type into the major region to define a more heavily doped region of the first conductivity type laterally encircled by the first lateral isolation region; and

forming (a) a semiconductive layer over the major region and (b) a transistor from the semiconductive layer such that part of each of the dopants diffuses into the semiconductor layer, the second dopant of the second conductivity type diffusing further into the semiconductive layer than the second dopant of the first conductivity type whereby the first lateral isolation region expands into the semiconductive layer to provide at least partial lateral junction isolation for the transistor while the vertical isolation region expands into the semiconductive layer to at least partially isolate the transistor from first conductivity type material of the major region, the dopant of the first conductivity type diffusing further into the semiconductive layer than the first dopant of the second conductivity type, a buffer region of the first conductivity type thereby being created by expansion of the more heavily doped region into the semiconductive layer so that the buffer region overlies the vertical isolation region and is encircled by the first lateral isolation region.

46. A method as in claim 45 further including the step of providing the semiconductive layer with an additional lateral isolation region of the second conductivity type meeting the first lateral isolation region such that the vertical and two lateral isolation regions completely isolate the transistor from the first conductivity type material of the major region.

47. A method as in claim 45 wherein the transistor is a bipolar transistor having a base of the second conductivity type.

48. A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

introducing first semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;

introducing second semiconductor dopant of the second conductivity type into the major region to define a first lateral isolation region of the second conductivity type continuous with the vertical isolation region, the second dopant having a greater diffusivity than the first dopant; and

forming (a) a semiconductive layer over the major region and (b) a bipolar transistor from the semiconductive layer such that part of each of the first and second dopants diffuses into the semiconductor layer, the second dopant diffusing further into the semiconductive layer than the first dopant whereby the first lateral isolation region expands into the semiconductive layer to provide at least partial lateral junction isolation for the transistor while the vertical isolation region expands into the semiconductive layer to at least partially isolate the transistor from first conductivity type material of the major region, the transistor having an emitter zone of the first conductivity type, a base zone of the second conductivity type, and continuous first and second collector zones of the first conductivity type, the first collector zone overlying the vertical isolation region, the forming step comprising;

forming a lower semiconductive layer that includes the first collector zone and a second lateral isolation region of the second conductivity type meeting the first lateral isolation region and surrounding the first collector zone; and

forming, over the lower semiconductive layer, an upper semiconductive layer that includes the second collector zone, the base zone, the emitter zone, and a third lateral isolation region of the second conductivity type meeting the second lateral isolation region and laterally surrounding the second collector zone.