Method of forming dual spacer for self aligned contact integration

• US 5,899,722 A
• Filed: 05/22/1998
• Issued: 05/04/1999
• Est. Priority Date: 05/22/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Jenn Ming
• Primary Examiner(s): Bowers, Charles L.
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/083,417
• Time in Patent Office: 347 Days
• Field of Search: 257/344, 257/388, 438/257, 438/258, 438/264, 438/303, 438/305, 438/307, 438/355, 438/637
• US Class Current: 438/305
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

In this invention two side wall spacers are applied to the vertical structure of a gate. The first spacer made of Si₃ N₄ provides for SAC (self aligned contact) definition and the second spacer made of SiO₂ is used for the definition of the LDD (lightly doped drain). The second spacer is the outer spacer and is anisotropically etched when the IPO (inter-poly-oxide) is etched to open a SAC contact area for second level polysilicon deposition. This allows a spacer width for the desired length of the LDD while providing a wider width for SAC contact. The SAC contact is not limited by the LDD spacer and the LDD spacer can be optimized without considering the SAC requirements. This invention is easily applied to SRAMS and DRAMS without extra masking.

Claims

1. A method of forming dual sidewall spacers for a semiconductor device, wherein some transistors have a shorter lightly doped drain, comprising the steps of:

a) forming a plurality of transistor gates on a semiconductor substrate, wherein each of the gates comprises a silicon nitride insulator above a polysilicon gate electrode,

b) ion implanting said semiconductor substrate using said gates as a mask to form lightly doped drain regions,

c) forming silicon nitride spacers on the sidewalls of each gate,

d) forming heavily doped first drain and first source regions in a non-memory region in said substrate using the silicon nitride spacer as a mask,

e) forming silicon oxide spacers over said silicon nitride spacers,

f) forming heavily doped second drain and second source regions in a memory region in said substrate using said silicon oxide spacers as a mask,

g) depositing an interpoly oxide layer over said substrate,

h) forming opening in said interpoly oxide layer in said non-memory region, exposing gate sidewall spacers,

i) removing said silicon oxide spacers from within said opening

j) forming a self aligned contact in said opening.

2. The method of claim 1, wherein forming said silicon nitride spacers comprises the steps of:

a) depositing a layer of silicon nitride over said gates and said substrate by low pressure chemical vapor deposition to a thickness of between about 600 and 1000 Angstroms,

b) anisotropically etching said silicon nitride to form said silicon nitride spacers.

3. The method of claim 1, wherein forming said silicon oxide spacers comprises the steps of:

a) depositing a layer of silicon oxide over said gates and said substrate by low pressure chemical vapor deposition to a thickness of between about 600 and 1000 Angstroms,

b) anisotropically etching said silicon oxide to form said silicon oxide spacers over said silicon nitride spacers.

4. The method of claim 1, wherein ion implanting forms P^- lightly doped drain regions, and forming heavily doped first and second drain and source regions is done with a P⁺ implant on an N substrate.

5. The method of claim 1, wherein ion implanting forms N^- lightly doped drain regions, and forming heavily doped first and second drain and source regions is done with an N⁺ implant on a P substrate.

6. The method of claim 1, wherein forming heavily doped source and drain regions can be done before forming said silicon oxide spacers over said silicon nitride spacers.

7. The method of claim 1, wherein forming said silicon oxide spacer protects the region and optimizes said transistor independent of the self aligned contact and forming the silicon nitride spacer optimizes said self aligned contact independent of said transistor.