Electronic circuit or board tester with compressed data-sequences

• US 5,899,961 A
• Filed: 03/04/1997
• Issued: 05/04/1999
• Est. Priority Date: 04/30/1996
• Status: Expired due to Term

• Current Assignee: Advantest Corporation
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Sundermann, Jens
• Primary Examiner(s): Barlow, John
• Assistant Examiner(s): SHAH, KAMINI S
• Application Number:
  US08/811,153
• Time in Patent Office: 791 Days
• Field of Search: 364/579, 364/580, 364/481, 371/27, 371/22.1, 371/22.2, 371/21.1, 324/761, 324/73.1, 702/117
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

This invention relates to electronic circuit testing and more particularly to an apparatus utilizing data compression techniques. An electronic circuit or board tester according to the invention includes one tester circuit with the combination of a sequencer and a vector-sequencer-memory per pin. A data-sequence, such as a loop to address the memory cells of an electronic memory one after the other in a predetermined chronological order, is applied to a pin of a device under test and is compressed in order to save memory space.

Claims

1. An electronic tester for testing an electronic memory, said tester including a plurality of tester circuits, and comprising:

a first memory for storing at least a compressed data-sequence which comprises an instruction and an operand, said instruction being a repeat instruction to repeat an operand for a predetermined number of clock cycles;

a sequencer, connected to said first memory via an address bus and a data bus, for controlling decompression of said compressed data-sequence to a decompressed data-sequence, and a transfer of said decompressed data-sequence to said electronic memory or to a first comparator which compares response data of said electronic memory with said decompressed data sequence, said decompressed data sequence being an address sequence which is applied to one address pin of the electronic memory, and data sequences of all tester circuits which are connected with address inputs of the electronic memory comprising sequences for addressing memory cells of said electronic memory, one after another; and

wherein said compressed data sequence is reiteratively executed and comprises;

for (address=0;

address<

n;

address=address+1);

A_X, A_X-1, A_X-2, . . . , A₂, A₁, A₀ =address and the address pin A₀ of said electronic memory is;

space="preserve" listing-type="equation">n/2×

"01"

with;

address=0;

first address

n;

uppermost address

address=address+1;

increment address by 1 each cycle

A_X, . . . , A₀ ;

address pins

n/2×

;

instruction to repeat "01" n/2 times.

2. An electronic circuit or board tester as recited in claim 1, wherein a totality of all data sequences of said tester circuits constitute one or more loops to address cells of said electronic memory, one after another in a predetermined order.

3. An electronic circuit or board tester as recited in claim 2, wherein said one or more loops constitute at least a part of a standard-test-pattern to address the cells of said memory in a predetermined chronological order.

4. An electronic circuit or board tester as recited in claim 1, wherein said compressed data sequence for the address pin A₁ is:

space="preserve" listing-type="equation">n/4×

(2×

"0";

2×

"1"),

wherein "0" is repeated 2 times, then "1" is repeated 2 times and then the foregoing is repeated n/4 times.

5. An electronic circuit or board tester for testing an electronic device, said tester including a plurality of tester circuits, and comprising:

a conductor for providing an electrical connection to said electronic device to be tested;

a first memory for storing at least a compressed data-sequence which comprises an instruction and an operand, said operand comprising a sequence of binary "0" and "1" data without any repetition of a part of said sequence of "0" and "1" data;

a sequencer, connected to said first memory via an address bus and a data bus, for controlling decompression of said compressed data-sequence to a decompressed data-sequence, and a transfer of said decompressed data-sequence to said electronic device or to a first comparator which compares response data of said electronic device with said decompressed data sequence;

each tester circuit being connected with another electrical connection to said electronic device to be tested; and

a first clock means for applying a timing signal to said sequencer.