Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency

• US 5,900,020 A
• Filed: 06/27/1996
• Issued: 05/04/1999
• Est. Priority Date: 06/27/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: Sequent Computer Systems, Inc. (International Business Machines Corporation)
• Inventors: Safranek, Robert J., Gilbert, Bruce M., Lovett, Thomas D., Joersz, Robert T.
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/678,372
• Time in Patent Office: 1,041 Days
• Field of Search: 711/141, 711/119, 711/120, 711/121, 711/147, 711/148, 711/167, 711/200.43, 711/200.44, 711/292, 711/874, 711/878, 711/879, 711/859, 711/735, 711/736
• US Class Current: 711/167
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request. The invalidate requests are added and removed from a processor'"'"'s outstanding invalidate list as they arise and are completed. An invalidate request is completed by notifying the nodes in a linked list related to the current invalidate request that data shared by the node is now invalid.

Claims

1. A method of maintaining memory consistency in a multinode computer, the method comprising the following steps:

queuing a current invalidate request by a processor;

acknowledging to the processor that the queued current invalidate request is complete before it has actually completed;

waiting for previous invalidate requests by the processor to complete; and

once the previous invalidate requests are complete, completing the queued current invalidate request.

2. The method of claim 1 wherein the memory consistency maintained is processor consistency.

3. The method of claim 1 wherein queuing the current invalidate request further includes adding the current invalidate request to a processor'"'"'s outstanding invalidate list.

4. The method of claim 3 wherein queuing the current invalidate request further includes removing the current invalidate request from the processor'"'"'s outstanding invalidate list after the current invalidate request is complete.

5. The method of claim 1 further including adding the current invalidate request to a current invalidate list after acknowledging to the processor that the current invalidate request is complete before it has completed.

6. The method of claim 5 further including removing the current invalidate request from the current invalidate list after the current invalidate request is complete.

7. The method of claim 1 wherein completing the current invalidate request comprises notifying the nodes in a linked list related to the current invalidate request that data shared by the nodes is invalid.

8. The method of claim 7 wherein notifying the nodes comprises relaying an invalidate request from a node in which the processor resides to each node in the list, the notification relayed from one node to the next until all nodes in the list have been notified.

9. The method of claim 1 further including:

receiving a read request for data on a first node from a second node;

determining if there is a pending invalidate request by a processor in the first node;

if so, delaying transmission of the data to the second node until the pending invalidate request is complete; and

if not, transmitting the data to the second node.

10. The method of claim 9 wherein the determining step includes taking a snapshot of a current invalidate list, the list containing acknowledgments to the processor that an invalidate request is complete before it has completed, to determine the pending invalidate requests.

11. The method of claim 9 including obtaining the requested data from storage in the first node before determining if there is a pending invalidate request.

12. The method of claim 1 including:

receiving an interrupt signal on a first node that an update of data is complete;

determining if there is a pending invalidate request;

if so, delaying transmission of the interrupt signal to a second node until the pending invalidate request is complete;

if not, transmitting the interrupt signal to the second node.

13. The method of claim 12 wherein the determining step includes taking a snapshot of a current invalidate list, the list containing acknowledgments to the processor that an invalidate request is complete before it has completed, to determine the pending invalidate requests.

14. A computer readable medium on which is stored a computer program for executing the steps of claim 1.

15. An apparatus for maintaining memory consistency in a multinode computer comprising:

a queue for queuing current invalidate requests by a processor; and

a protocol engine for;

acknowledging to the processor that a current invalidate request is complete before it has actually completed;

waiting for previous invalidate requests by the processor to complete; and

once the previous invalidate requests are complete, completing the queued current invalidate request.

16. A computer readable medium on which is stored a computer program for executing the steps of claim 15.

17. A method of maintaining memory consistency in a multinode computer, the method comprising the following steps:

receiving a signal from a processor or input/output (I/O) device in a first node which is ready for transmission to a second node;

determining if there is a pending invalidate request by the processor or I/O device;

if so, delaying transmission of the signal to the second node until the pending invalidate request is complete; and

if not, transmitting the signal to the second node.

18. The method of claim 17 wherein the signal ready for transmission is data supplied by the processor in response to a read request from the second node.

19. The method of claim 17 wherein the signal ready for transmission is an interrupt signal indicating that an update of data is complete.

20. The method of claim 17 wherein the determining step further includes taking a snapshot of a current invalidate list.

21. An apparatus for maintaining memory consistency in a multinode computer comprising:

a current invalidate list containing pending invalidate requests by a processor or I/O device; and

a protocol engine for;

receiving a signal from a processor or input/out (I/O) device in a first node which is ready for transmission to a second node;

determining from the list if there is a pending invalidate request;

if so, delaying transmission of the signal to the second node until the pending invalidate request determined from the list is complete; and

if not, transmitting the signal to the second node.

22. A method of maintaining memory consistency in a multiprocessor computer, the method comprising the following steps:

queuing a current invalidate request by a processor;

acknowledging to the processor that the queued current invalidate request is complete before it has actually completed;

waiting for a previous invalidate request by the processor to complete; and

completing the queued current invalidate request once the previous invalidate request is complete.

23. An apparatus for maintaining memory consistency in a multiprocessor computer comprising:

a queue for queuing current invalidate requests by a processor;

means for acknowledging to the processor that a queued current invalidate request is complete before it has actually completed;

means for waiting for a previous invalidate request by the processor to complete; and

means for completing the queued current invalidate request once the previous invalidate request is complete.