Active pixel sensor using CMOS technology with reverse biased photodiodes

• US 5,900,623 A
• Filed: 08/11/1997
• Issued: 05/04/1999
• Est. Priority Date: 08/11/1997
• Status: Expired due to Term

• Current Assignee: Chrontel, Inc.
• Original Assignee: Chrontel, Inc.
• Inventors: Yen, King Cheung, Tsang, Randy P.L., Donovan, Timothy J., Tse, Lawrence Tze-Leung
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US08/909,162
• Time in Patent Office: 631 Days
• Field of Search: 250/208.1, 250/214 R, 250/214 P, 250/214 SW, 250/214.1, 356/218, 356/222, 348/308, 348/294, 348/298, 257/291, 257/298
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

An active pixel sensor implemented with CMOS technology that employs a plurality of photocells, each including a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode. Each photocell includes a switching network that couples the photocurrent to the storage node only during the integration period while ensuring that a relatively constant voltage is maintained across the photodiode during integration and non-integration periods. The transistors in the switching network operate in a forward active subthreshold region, ensuring linear operation and the diode voltage is clamped to a small positive voltage so that the diode is always reverse-biased. A source-follower generates a output signal correlated to the charge on the storage node that is coupled to column output circuitry that samples the signal. An operational scheme is employed wherein the storage node is first set to a defined voltage, the photocurrent is allowed to discharge the storage node and then the remaining charge coupled as a first signal to the column output circuitry, which samples and stores the first signal. The storage node is then reset to the same defined voltage and the resulting charge on the storage node is coupled as a second signal to the column output circuitry. The column output circuitry computes the difference of the first and second signals, which provides a reliable measure of the photocurrent during the integration period.

Claims

1. An active pixel sensor using CMOS technology, comprising:

a plurality of photocells, each configured to sense illumination falling on a respective region of the active pixel sensor and to generate an output signal corresponding to the sensed illumination, wherein each of the photocells includes;

a reverse-biased photodiode that generates a photocurrent that is proportional to the illumination falling on the photocell; and

a storage device coupled to and distinct from the photodiode with a stored charge that is discharged during an integration period as a function of the photocurrent, the amount of the stored charge discharged during the integration period determining the output signal.

2. The active pixel sensor of claim 1, wherein the photodiode and the storage device are configured so that the photocell provides high electron-to-voltage gain.

3. The active pixel sensor of claim 1, wherein the storage device is a capacitor implemented as a MOS transistor with grounded source and drain operating in the triode region.

4. The active pixel sensor of claim 1, wherein a relatively-constant, reverse bias diode voltage is maintained across the photodiode during the integration period as well as between successive integration periods.

5. The active pixel sensor of claim 4, wherein the reverse bias diode voltage is clamped to a small positive voltage under normal operating conditions.

6. The active pixel sensor of claim 5, wherein the small positive voltage is approximately 1.5 V.

7. The active pixel sensor of claim 4, further comprising a switching network that includes:

a first n-channel transistor that is configured to couple the cathode of the photodiode to a small, positive voltage only during a non-integration period that is complementary to the integration period and enables the photocurrent generated during the non-integration period to bypass the storage device and instead flow through the first transistor; and

a second n-channel transistor that is configured to couple the cathode of the photodiode to the small, positive voltage only during the integration period and enables the photocurrent generated during the integration period to discharge the storage device instead of flowing through the first transistor.

8. The active pixel sensor of claim 7, wherein the reverse bias diode voltage is clamped to a second small positive voltage under normal operating conditions.

9. The active pixel sensor of claim 8, wherein the second small positive voltage is approximately 1.5V.

10. The active pixel sensor of claim 4, wherein the reverse-bias diode voltage is clamped to a small positive voltage that it is no less than VBOT-V_gs, where VBOT is a regulated voltage coupled to the gates of the first and second n-channel transistors during the non-integration and integration periods and V_gs is the gate-source voltage of the first and second transistors, thereby preventing anti blooming on a display coupled to the active pixel sensor.

11. The active pixel sensor of claim 7, wherein:

the first transistor has a gate, drain and source coupled to an SCB signal, a reset voltage supply node and the cathode of the photodiode; and

the second transistor has a gate, drain and source coupled to an SC signal, a storage node and the cathode of the photodiode;

wherein the storage node is coupled to one terminal of the storage capacitor, the SC and SCB signals are substantially-complementary signals that are generated so that the first and second transistors operate in the active sub-threshold region.

12. The active pixel sensor of claim 11, wherein the SC and SCB signal levels are generated so that, at the beginning of the integration period, the SCB signal makes a high to low transition just after the SC signal makes a low to high transition, ensuring that the diode voltage remains stable during transitions between the non-integration and integration periods.

13. The active pixel sensor of claim 11, wherein the SC and SCB signal levels are generated so that at the end of the integration period, the SC signal makes a high to low transition just after the SCB signal makes a low to high transition, ensuring that the diode voltage remains stable during transitions between the integration and non-integration periods.

14. The active pixel sensor of claim 11, wherein the SC and SCB signal levels are derived from a bandgap reference voltage.

15. The active pixel sensor of claim 11, wherein the first and second transistors are comparatively large devices that carry very small drain currents when operating in the active, sub-threshold mode.

16. The active pixel sensor of claim 11, wherein the reset voltage supply node provides a VRST voltage.

17. The active pixel sensor of claim 16, further comprising a reset transistor configured to pull the storage node up to the VRST voltage in response to the activation of a reset (RS) signal coupled to the gate of the reset transistor.

18. The active pixel sensor of claim 17, wherein the RS signal is at a positive voltage level that is higher than the VRST voltage by at least the threshold voltage of the reset transistor.

19. The active pixel sensor of claim 18, wherein the RS signal is generated by a charge pump circuit.

20. The active pixel sensor of claim 9, further comprising a control signal generation (CSG) circuit configured to generate the SC and SCB signals, the CSG circuit being responsive to an integrate signal and a bandgap reference and including:

a biasing network that, based on the bandgap reference, generates a top reference voltage (VTOP) level and a bottom reference voltage (VBOT) level; and

a combinational network that, in response to activation of the integrate signal, generates the SC and SCB signals so that the SC signal rises to the VTOP level shortly before the SCB signal fails to the VBOT level, and, in response to the deactivation of the integrate signal, generates the SC and SCB signals so that the SCB signal rises to the VTOP level shortly before the SC signal falls to the VBOT level.

21. The active pixel sensor of claim 20, wherein the VTOP level is at approximately 2.1 volt and the VBOT level is at approximately 1.5 volt.

22. The active pixel sensor of claim 1, further comprising column output circuitry configured:

in a first mode to sample and hold a first signal corresponding to the amount of charge on the storage node at the end of the integration period, including parasitic effects; and

in a second mode to;

sample a second signal corresponding to the charge at the storage node at the beginning of the previous integration period, including the parasitic effects, and

subtract the first signal from the second signal so as to provide the output signal representing just the charge discharged from the storage node during the integration period.

23. The active pixel sensor of claim 22, wherein the column output circuitry comprises:

a voltage bias transistor with a drain, gate and source coupled respectively to a column output signal, a bias control signal and a bias voltage, such that, when the bias control signal is asserted, the drain is set to the bias voltage;

a column amplifier with an input coupled to the drain of the bias transistor; and

a sample and hold block with an input coupled to the output of the column amplifier and an output that forms the active pixel sensor output signal;

wherein;

in the first mode the sample and hold block stores the first signal value equaling Vsig+Vmid+Voffset, where "Vsig" represents the amount of the stored charge discharged during the integration period, "Vmid" is the bias voltage and "Voffset" represents voltage offsets in the pixel sensor; and

in the second mode;

the bias signal is asserted, causing the input of the column amplifier to go to Vmid while the output of the column amplifier and the input of the sample and hold block go to the second signal value equaling Vmid+Voffset bias; and

the sample and hold block subtracts the second signal value from the first signal value, producing the output signal of Vsig.

24. The active pixel sensor of claim 22, further comprising:

a source follower coupled to the storage node that provides a signal corresponding to the output signal on its source; and

an output switching transistor with a gate, drain and source coupled, respectively, to a ROW enable signal, the source of the source follower and the input of the column output circuitry.

25. The active pixel sensor of claim 24, wherein the column output circuitry comprises a sample and hold capacitor implemented as a MOSFET transistor having a gate employed as one terminal of the capacitor and shorted gate and drain employed as the other terminal of the capacitor, one of the terminals being coupled to the source of the output switching transistor and the other of the terminals being coupled to the input of a column amplifier.

26. The active pixel sensor of claim 24, further comprising a reset transistor configured to pull the storage node up to a defined voltage level in response to the activation of a reset (RS) signal coupled to the gate of the reset transistor.

27. The active pixel sensor of claim 26, wherein:

(1) just before the beginning of the integration period, the RS signal is pulsed, causing the reset transistor to set the storage node to the defined voltage level;

(2) the SC signal is asserted to initiate the integration period during which the charge on the storage node is discharged;

(3) the SC signal is deasserted after a shutter period to end the integration period;

(4) the ROW signal is asserted to couple a first signal corresponding to the charge on the storage node at the end of the integration period, including parasitic effects, to column output circuitry, which samples and holds the first signal;

(5) the ROW signal is deasserted;

(6) the RS signal is pulsed, causing the reset transistor to set the storage node to the defined voltage level; and

(7) the ROW signal is asserted to couple a second signal corresponding to the charge on the storage node at the beginning of the integration period, including the parasitic effects, to the column output circuitry, which samples the second signal and subtracts the first signal from the second signal so as to provide a corrected output signal.

28. An active pixel sensor method for use in each of a plurality of photocells, each configured to sense illumination falling on a respective region of an active pixel sensor and to generate an output signal corresponding to the sensed illumination, the method comprising the steps of:

storing a charge on a storage device within the photocell;

generating a photocurrent that is proportional to the illumination falling on the photocell using a photodiode within the photocell, the photodiode being distinct from the storage device; and

discharging the storage node during an integration period as a function of the photocurrent, the amount of the stored charge discharged during the integration period determining the output signal.

29. The method of claim 28, further comprising the step of:

maintaining a relatively-constant, reverse bias diode voltage across the photodiode during the integration period as well as between successive integration periods.

30. The method of claim 29, further comprising the steps of:

coupling during a non-integration period that is complementary to the integration period the cathode of the photodiode to a small, positive voltage in such a manner that the photocurrent generated during the non-integration period bypasses the storage device; and

coupling during the integration period the cathode of the photodiode to the small, positive voltage in such a manner that the photocurrent generated during the integration period discharges the storage device.

31. The method of claim 30, wherein the coupling of the photodiode to the diode voltage during the non-integration mode is determined by an SCB signal and the coupling of the photodiode to the diode voltage during the integration mode is determined by an SC signal.

32. The method of claim 31, wherein the step of generating the SC and SCB signals comprises generating the SC and SCB signals, so that, at the beginning of the integration period, the SCB signal makes a high to low transition just after the SC signal makes a low to high transition, ensuring that the diode voltage remains stable during transitions between the non-integration and integration periods.

33. The method of claim 31, wherein the step of generating the SC and SCB signals comprises generating the SC and SCB signals, so that, at the end of the integration period, the SC signal makes a high to low transition just after the SCB signal makes a low to high transition, ensuring that the diode voltage remains stable during transitions between the integration and non-integration periods.

34. The method of claim 31, wherein the step of generating the SC and SCB signals comprises:

generating a top reference voltage (VTOP) level and a bottom reference voltage (VBOT) level; and

in response to activation of an integrate signal, generating the SC and SCB signals so that the SC signal rises to the VTOP level shortly before the SCB signal falls to the VBOT level, and, in response to the deactivation of the integrate signal, generating the SC and SCB signals so that the SCB signal rises to the VTOP level shortly before the SC signal falls to the VBOT level;

the SCB and SC signals being respectively coupled to first and second transistors configured to couple the photodiode to the diode voltage in response to activation of the SCB and SC signals, respectively.

35. The method of claim 34, wherein the VTOP level is at approximately 2.1 volt and the VBOT level is at approximately 1.5 volt.

36. The method of claim 28, further comprising the steps of:

in a first mode, sampling and holding a first signal corresponding to the amount of charge on the storage node at the end of the integration period, including parasitic effects; and

in a second mode;

sampling a second signal corresponding to the charge at the storage node at the beginning of the previous integration period, including the parasitic effects, and

subtracting the first signal from the second signal so as to provide the output signal representing just the charge discharged from the storage node during the integration period.

37. The method of claim 36, wherein the photocell includes column output circuitry comprising:

a voltage bias transistor with a drain, gate and source coupled respectively to a column output signal, a bias control signal and a bias voltage, such that, when the bias control signal is asserted, the drain is set to the bias voltage;

a column amplifier with an input coupled to the drain of the bias transistor; and

a sample and hold block with an input coupled to the output of the column amplifier and an output that forms the active pixel sensor output signal;

wherein;

in the first mode the sample and hold block stores the first signal value equaling Vsig+Vmid+Voffset, where "Vsig" represents the amount of the stored charge discharged during the integration period, "Vmid" is the bias voltage and "Voffset" represents voltage offsets in the pixel sensor; and

in the second mode;

the bias signal is asserted, causing the input of the column amplifier to go to Vmid while the output of the column amplifier and the input of the sample and hold block go to the second signal value equaling Vmid+Voffset bias; and

the sample and hold block subtracts the second signal value from the first signal value, producing the output signal of Vsig.

38. The method of claim 36, comprising the steps of:

(1) just before the beginning of the integration period setting the storage node to a defined voltage level;

(2) initiating the integration period during which the charge on the storage node is discharged;

(3) ending the integration period;

(4) coupling a first signal corresponding to the charge on the storage node at the end of the integration period, including parasitic effects, to column output circuitry, which samples and holds the first signal;

(5) resetting the storage node to the defined voltage level; and

(6) coupling a second signal corresponding to the charge on the storage node at the beginning of the integration period, including the parasitic effects, to the column output circuitry, which samples the second signal and subtracts the first signal from the second signal so as to provide a corrected output signal.